Results 171 to 180 of about 6,132 (187)
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Static Analysis of Transaction-Level Communication Models
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2008We propose a methodology for the early estimation of communication implementation choice effects, starting from an abstract transaction-level system model (TLM). The reference version of the TLM considered is the Open SystemC initiative library. The methodology is based on the computation of metrics that abstract useful information from the initial ...
AGOSTA, GIOVANNI +2 more
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Dynamic power estimation using Transaction Level Modeling
Microelectronics Journal, 2018Abstract Designing an efficient (from performance and power points of view) system on chip (SoC) is one of the main challenges nowadays. This paper introduces a methodology that uses Transaction Level Modeling (TLM) to accelerate the simulation time for power estimation allowing fast SoC evaluation.
Amr Baher +8 more
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Multi-level fault modeling for transaction-level specifications
Proceedings of the 19th ACM Great Lakes symposium on VLSI, 2009Fault modeling is a fundamental element for several activities, ranging from off- and on-line testing, to fault tolerance and dependability-aware design. These activities are carried out during various design phases, dealing with specifications at different abstraction levels.
BELTRAME, GIOVANNI +2 more
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Adaptive Interconnect Models for Transaction-Level Simulation
2009Transaction level models are constructed for efficient simulation of complex embedded systems and systems-on-chip. Traditionally, the use case of a transaction level model dictates its accuracy and abstraction level, which are fixed during simulation. Although the chosen level of accuracy may be required in some intervals, in some other intervals the ...
Rauf Salimi Khaligh, Martin Radetzki
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Exploring Design Space Using Transaction Level Models
2005This paper presents THU-SOC, a new methodology and tool dedicated to explore design space by executing full-scale SW application code on the transaction level models of the SoC platform. The SoC platform supports alternative Transaction Level Models (TLMs), bus-functional model and bus-arbitration model, which enables it to cooperate with different ...
Youhui Zhang +3 more
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SystemC transaction level models and RTL verification
2006 43rd ACM/IEEE Design Automation Conference, 2006This paper describes how systems companies are adopting SystemC transaction level models for system on chip design and verification, and how these transaction level models are being reused for RTL verification. The paper discusses how the task of system verification is changing as systems become more complex and it discusses how companies are striving ...
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An Enhanced SystemC UML Profile for Modeling at Transaction-Level
2008This chapter describes a UML2 profile for the SystemC language, which takes into account the language improvements as specified in the IEEE 1666 SystemC Standard and effectively provided in the SystemC 2.2 simulator as foundation for Transaction-Level Modeling (TLM).
Bocchio, S. +3 more
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Transaction-Level Modeling and Refinement Using State Charts
2013Since State Charts have been introduced, they have proven to be of great use in the design of complex reactive systems. Previous work has shown that, in hardware design, they can be successfully used for transaction-level modeling as well as for cycle-callable systems. This paper presents a structure-preserving refinement approach for State Charts that
Rainer Findenig +2 more
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Transaction Level Model Automation for Multicore Systems
2010Model based verification has been the bedrock of electronic design automation. Over the past several years, system modeling has evolved to keep up with improvements in process technology fueled by Moore’s law. Modeling has evolved to keep up with the complexity of applications resulting in various levels of abstractions.
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