Results 41 to 50 of about 1,914,541 (354)
DHTM: Durable Hardware Transactional Memory
International Symposium on Computer Architecture, 2018 The emergence of byte-addressable persistent (non-volatile) memory provides a low latency and high bandwidth path to durability. However, programmers need guarantees on what will remain in persistent memory in the event of a system crash.
A. Joshi +3 more
semanticscholar +1 more source
Simplifying Transactional Memory Support in C++
ACM Transactions on Architecture and Code Optimization (TACO), 2019 C++ has supported a provisional version of Transactional Memory (TM) since 2015, via a technical specification. However, TM has not seen widespread adoption, and compiler vendors have been slow to implement the technical specification. We conjecture that
Pantea Zardoshti +4 more
semanticscholar +1 more source
On the Semantics of Snapshot Isolation [PDF]
, 2018 Snapshot isolation (SI) is a standard transactional consistency model used in databases, distributed systems and software transactional memory (STM).
A Cerone +11 more
core +2 more sources
Romulus: Efficient Algorithms for Persistent Transactional Memory
ACM Symposium on Parallelism in Algorithms and Architectures, 2018 Byte addressable persistent memory eliminates the need for serialization and deserialization of data, to and from persistent storage, allowing applications to interact with it through common store and load instructions.
Andreia Correia, P. Felber, P. Ramalhete
semanticscholar +1 more source
IEEE Access, 2020 Efficient resource optimization is critical to manage the velocity and volume of real-time streaming data in near-real-time data warehousing and business intelligence.
M. Asif Naeem +5 more
doaj +1 more source
Avoiding Publication and Privatization Problems on Software Transactional Memory [PDF]
, 2011 This paper presents a new approach to exclude problems arising from dynamically switching between protected concurrent and unprotected single-threaded use of shared data when using software transactional memory in OO languages such as Java.
Machens, Holger, Turau, Volker
core +1 more source
HaTS: Hardware-Assisted Transaction Scheduler [PDF]
, 2020 In this paper we present HaTS, a Hardware-assisted Transaction Scheduler. HaTS improves performance of concurrent applications by classifying the executions of their atomic blocks (or in-memory transactions) into scheduling queues, according to their so ...
Chen, Zhanhao +4 more
core +1 more source
Leveraging Hardware Transactional Memory for Cache Side-Channel Defenses
ACM Asia Conference on Computer and Communications Security, 2018 A program's use of CPU caches may reveal its memory access pattern and thus leak sensitive information when the program performs secret-dependent memory accesses.
Sanchuan Chen +6 more
semanticscholar +1 more source
Shared cognition: a review on transactional memory [PDF]
Alteridad : Revista de Educación, 2010 La memoria transaccional es un sistema cognitivo interdependiente de codificación, almacenamiento, recuperación y comunicación de información que condensa el conocimiento que poseen los individuos, en una conciencia compartida por el grupo sobre quién ...
Katia Puente-Palacios, Aline Severino
doaj
Clock gate on abort: Towards energy-efficient hardware transactional memory [PDF]
, 2009 Transactional Memory (TM) is an emerging technology which promises to make parallel programming easier compared to earlier lock based approaches. However, as with any form of speculation, Transactional Memory too wastes a considerable amount of energy ...
Cristal Kestelman, Adrián +4 more
core +1 more source