Results 71 to 80 of about 3,793 (226)
Simulation study on high-linearity GaN HEMT featuring graded-composition composite channel
This work proposes and simulates a high-linearity GaN HEMT device using Technology Computer Aided Design (TCAD). The device features a composite channel based on graded-composite AlGaN and InGaN layers.
Li Shiquan +3 more
doaj +1 more source
Wafer‐Scale 3D Integration for High‐Density Multi‐Valued Neuromorphic Logic
Wafer‐scale 3D vertically integrated multi‐valued logic (MVL) circuits are realized by monolithically integrating a Te/IGZO heterojunction FET with an engineered Te pull‐up FET. Heterointerface‐mediated transport and optimized current matching enable stable ternary operation, while vertical stacking reduces circuit footprint and interconnect complexity,
Chang‐Hyeon Kim +5 more
wiley +1 more source
Investigating Pocket-Engineered Tree-Based NSFETs With Asymmetric Spacers
This work investigates the impact of pocket doping concentration variation from $1 \times 10^{17}$ to $5 \times 10^{18}$ cm−3 on the DC, analog, and RF performance of a proposed FET device, demonstrating that tailored pocket engineering ...
Akash Mandal +5 more
doaj +1 more source
Intrinsically stretchable OECTs enable bifunctional operations via gate engineering. Polarizable Ag/AgCl gates provide volatile sensing, while Au gates enable non‐volatile memory. The SEBS‐blended channel maintains performance under strain, supporting reliable signal transduction.
Jiyong Yoon +8 more
wiley +1 more source
ABSTRACT Layered 2D materials are considered as promising for memristive applications due to their ultimate vertical scalability compared to conventional semiconductor films and pronounced hysteresis properties. Bias‐resolved Raman and Photoluminescence mapping is used to quantify strain from phonon shifts and carrier density from the exciton‐trion ...
Vladislav Kurtash +4 more
wiley +1 more source
Resistive memory devices are explored for operation at extremely low temperatures relevant to quantum computing. The study reveals how transistor behavior strongly influences memory performance under cryogenic conditions and introduces an optimized programming strategy.
Emilio Pérez‐Bosch Quesada +11 more
wiley +1 more source
A novel strategy is used to fabricate multi‐threshold‐voltage (multi‐Vth) IGZO FETs via continuous‐wave laser scanning annealing (CW‐LSA). By tuning the laser power and scan speed, low, standard, and high Vth values of 0.22, 0.42, and 0.62 V, respectively, were achieved on a single wafer with excellent uniformity (coefficient of variation: 2.17%–6.61%).
Jun‐Hyeok Choi +8 more
wiley +1 more source
An Ultra-Low-Voltage Transconductance Stable and Enhanced OTA for ECG Signal Processing
In this paper, a rail-to-rail transconductance stable and enhanced ultra-low-voltage operational transconductance amplifier (OTA) is proposed for electrocardiogram (ECG) signal processing. The variation regularity of the bulk transconductance of pMOS and
Yue Yin +7 more
doaj +1 more source
ABSTRACT Machine learning and Artificial Intelligence (AI) tasks have stretched traditional hardware to its limits. In‐hardware computation is a novel approach that aims to run complex operations, such as matrix–vector multiplication, directly at the device level for increased efficiency.
Juan P. Martinez +10 more
wiley +1 more source
Digitally Programmable Integrator and Differentiator
Digitally programmable integrator and differentiator circuits are presented. Each circuit uses at most one operational amplifier, two operational transconductance amplifiers, and one capacitor.
Abdulrahman Khalaf Al-Ali +2 more
doaj +1 more source

