Results 141 to 150 of about 3,453 (181)

Viterbi algorithm motives in turbo decoding

IEEE Information Theory Workshop, 2005., 2005
This work addresses the problem of decoding turbo convolutional codes. In particular, it is concerned with the question of how maximum likelihood sequence estimation (MLSE), in the shape of the Viterbi algorithm (VA), can be utilized in the framework of turbo decoding. It is shown that the conventional VA, which is a soft-input hard-output decoder, can
M. Kerner, O. Amrani
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Iterative Viterbi Algorithm: Implementation Issues

IEEE Transactions on Wireless Communications, 2004
We address several issues for implementing the iterative Viterbi decoder. We show that 3-bit branch metric quantization, 7- or 8-bit state metric precision, and a survivor length of five times the constraint length yields little degradation for the iterative Viterbi algorithm (IVA).
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List Viterbi algorithms for wireless systems

VTC2000-Spring. 2000 IEEE 51st Vehicular Technology Conference Proceedings (Cat. No.00CH37026), 2002
The conventional list Viterbi algorithm (LVA) produces a list of the L best output sequences over a certain block length in decoding a terminated convolutional code. We show in this paper that the list Viterbi algorithm with a sufficiently long list is the optimum maximum likelihood decoder for the concatenated pair of a convolutional code and a cyclic
B. Chen, C.-E.W. Sundberg
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Adaptive block-length partitioned Viterbi algorithm

2015 IEEE 14th Canadian Workshop on Information Theory (CWIT), 2015
To improve wireless system performance using co-channel signals and multiple receiver antennas, we develop a new adaptive block-length partitioned Viterbi algorithm (ABL-PVA) receiver for the MIMO frequency-selective fading channel. The classic PVA has a trellis detector for each transmit antenna and feeds back tentative decisions between these trellis
Mohamed Haroun, Sebastien Roy
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A hardware efficient parallel Viterbi algorithm

International Conference on Acoustics, Speech, and Signal Processing, 2002
A hardware efficient block processing scheme is proposed for concurrent implementation of the Viterbi algorithm. The throughput increase is proportional to the increase in hardware complexity at the expense of latency. Advantages of the algorithm over other parallel schemes are that the reduction of the information rate due to bit stuffing at the ...
P.J. Black, T.H.-Y. Meng
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Software solutions for the Viterbi algorithm

VLSI Signal Processing, VIII, 2002
Efficient software implementations of the Viterbi algorithm on two new generation processors, /spl mu/PD7701x and V830 are discussed. /spl mu/PD7701x is a 16-bit fixed point general purpose DSP which includes eight 40-bit general purpose registers, highly parallel operation capability, and conditional execution capability.
M. Ikekawa, I. Kuroda
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A Personal History of the Viterbi Algorithm

IEEE Signal Processing Magazine, 2006
This paper describes how Andrew J. Viterbi developed a non-sequential decoding algorithm which proved useful in showing the superiority of convolutional codes over block codes for a given degree of decoding complexity. The Viterbi algorithm is now used in most digital cellular phones and digital satellite receivers as well as in such diverse fields as ...
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On the Viterbi decoding algorithm

IEEE Transactions on Information Theory, 1969
A new interpretation of the Viterbi decoding algorithm based on the state-space approach to dyamical systems is presented. In this interpretation the optimum decoder solves a generalized regulator control problem by dynamic programming techniques.
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Viterbi algorithm for detecting DDoS attacks

2015 IEEE 40th Conference on Local Computer Networks (LCN), 2015
Distributed denial of service attacks aim at making a given computational resource unavailable to users. A substantial portion of commercial Intrusion Detection Systems operates only with detection techniques based on rules for the recognition of pre-established behavioral patterns (called signatures) that can be used to identify these types of attacks.
Wilson Bongiovanni, Adilson E. Guelfi, Elvis Pontes, A. A. A. Silva, Fen Zhou, Sergio Takeo Kofuji   +5 more
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Pipelined architectures for the Viterbi algorithm

TENCON '97 Brisbane - Australia. Proceedings of IEEE TENCON '97. IEEE Region 10 Annual Conference. Speech and Image Technologies for Computing and Telecommunications (Cat. No.97CH36162), 2002
The main part of the Viterbi algorithm is a nonlinear feedback loop which presents a bottleneck for high-speed implementations. We propose four different solutions for increasing the computation speed of the Viterbi algorithm, three of them are based on the utilization of pipelined systems combined with efficient scheduling methodologies and the other ...
M. Boo, J.D. Brugera
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