Results 141 to 150 of about 794,689 (198)
Generation of High Voltage with Voltage Multiplier for Insulation Testing
, 2020 {"references": ["Waluyo, Syahrial, Sigit Nugraha, Yudhi Permana J. R. (2015), \"Miniature prototype design and implementation of modified multiplier circuit dc high voltage generator\", Inter. J. of Elect. Eng. & Tech., Volume 6, Issue 1, pp. 01\u201312", "Meghana G Naik, CH. Jayavardhana Rao, Dr. Venugopal.
K. Prasath +3 more
openaire +3 more sources
Some of the next articles are maybe not open access.
Related searches:
Related searches:
Useful multipliers for low-voltage applications
2002 IEEE International Symposium on Circuits and Systems. Proceedings (Cat. No.02CH37353), 2003Two useful low voltage multipliers are presented in this paper. They employ only two transistors between the rails and perform four-quadrant multiplication. These circuits are based on the V/sub gs//sup 2/ technique, and use MOS transistors in saturation in order to achieve squaring of the differential inputs.
Brent Maundy, Peter B. Aronhime
openaire +2 more sources
CMOS voltage-mode analog multiplier
2006 IEEE International Symposium on Circuits and Systems, 2006This paper proposes a CMOS voltage-mode four-quadrant analog multiplier. It is based on a pair of diode-connected MOS transistor that is biased with a constant current source, and a CMOS voltage difference circuit. Simulation results shows that the linear range is /spl plusmn/400 mV with the linearity error of 0.8% and the harmonic distortion of 0.62%.
Boonchai Boonchu, Wanlop Surakampontorn
openaire +1 more source
A 1.5 V CMOS voltage multiplier
1998 IEEE International Conference on Electronics, Circuits and Systems. Surfing the Waves of Science and Technology (Cat. No.98EX196), 2002New and simple CMOS multiplier powered with a 1.5 V supply is presented. It has a 3-dB cut-off frequency at 140 MHz, and reaches its 1-dB compression point for 140 mV/sub pp/ of input voltage. Moreover, its particular topology makes it useful for an integration in fully digital ICs.
Gianluca Giustolisi +2 more
openaire +1 more source
Reduction of voltage drop and ripple in voltage multipliers
2015 17th European Conference on Power Electronics and Applications (EPE'15 ECCE-Europe), 2015In this paper we present a novel topology for high voltage generation based on the widely used Half-Wave Cockcroft-Walton voltage multiplier. The proposed topology consists of several voltage multiplying sections fed separately at their inputs and whose output voltages are summated across the load. Using the proposed topology we can attain over m times
Se Hyun Park +2 more
openaire +1 more source
Review of Scientific Instruments, 1962
A suggested multistage high voltage multiplier design utilizing a low duty cycle 10-kc pulse drive has been built, tested, and found reliably operable at twice the dc voltage gain per rectifier stage of conventional sine wave drive Cockcroft-Walton multipliers.
openaire +1 more source
A suggested multistage high voltage multiplier design utilizing a low duty cycle 10-kc pulse drive has been built, tested, and found reliably operable at twice the dc voltage gain per rectifier stage of conventional sine wave drive Cockcroft-Walton multipliers.
openaire +1 more source
Voltage multiplier with output stabilization
38th Midwest Symposium on Circuits and Systems. Proceedings, 2002In this paper we present a charge-pump voltage multiplier with output regulation. Using this scheme we designed two voltage sources suitable for generating the high voltages required to program a flash memory using a single 5 V power supply. The first circuit can drive the selected memory word-line with the required voltage (10.5 V). The second circuit
C. Calligaro, P. Malcovati, G. Torelli
openaire +1 more source
Characteristics of Voltage-Multiplying Rectifiers
Proceedings of the IRE, 1944A combined experimental and theoretical analysis is used to determine the manner in which the characteristics of the half-wave and full-wave voltage-doubling rectifier circuits depend upon the resistance of the diodes and upon the load resistance. The characteristic curves reproduced include those for the load voltage, ripple voltage, and maximum tube ...
D.L. Waidelich, C.L. Shackelford
openaire +1 more source
Multiplier offset voltages in adaptive arrays
1972 Antennas and Propagation Society International Symposium, 1972This paper examines the effects of multiplier offset voltages in adaptive arrays. Multiplier offset voltages arise when active circuits are used to implement the error-by-signal multipliers required in an array based on the LMS algorithm. These offset voltages are known from experimental work to have a strong effect on array performance.
openaire +1 more source
A 1 MHz voltage multiplier design
2002 IEEE International Symposium on Circuits and Systems. Proceedings (Cat. No.02CH37353), 2003A circuit design tutorial is presented for a general purpose capacitor charge pump voltage multiplier. Circuit design equations for ideal and non-ideal MOSFET switches are developed. Using the equations, a practical implementation at 1 MHz operating frequency is then presented. Experimental results are used to confirm the validity of the design process.
openaire +1 more source