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A novel energy efficient 4-bit vedic multiplier using modified GDI approach at 32 nm technology. [PDF]
HeliyonNishanth Rao K +7 more
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A Fully Integrated Memristive Chaotic Circuit Based on Memristor Emulator with Voltage-Controlled Oscillator. [PDF]
Micromachines (Basel)Duan Z +6 more
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Topolectrical space-time circuits. [PDF]
Nat CommunZhang W, Cao W, Qian L, Yuan H, Zhang X.
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Model predictive control based on single-phase shift modulation for triple active bridge DC-DC converter. [PDF]
Sci RepAdam AHA, Chen J, Xu M, Kamel S, Ali G.
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Transformer-less high gain DC-DC converter design and analysis for fuel cell vehicles. [PDF]
Sci RepAljafari B +3 more
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Low Voltage Analogue Multiplier
APCCAS 2006 - 2006 IEEE Asia Pacific Conference on Circuits and Systems, 2006With the reduction in supply voltages in order to minimize power dissipation, arises the need for a low voltage analogue multiplier. Developed is a multiplier that operates at as low a voltage as that required to bias a single n-MOS transistor by utilizing CMOS, as against the conventional multipliers which use either n-MOS or p-MOS transistor in the ...
Saurabh Singh, K. Radhakrishna Rao
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Review of Scientific Instruments, 1999
A pulse voltage multiplier is presented. The device consists of a set of transmission lines connected in parallel at the entry and connected in series at the end. The multiplication factor can become equal to twice the number of transmission lines, depending on the conditions at the entry of the device.
Leopoldo Soto, Luis Altamirano
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A pulse voltage multiplier is presented. The device consists of a set of transmission lines connected in parallel at the entry and connected in series at the end. The multiplication factor can become equal to twice the number of transmission lines, depending on the conditions at the entry of the device.
Leopoldo Soto, Luis Altamirano
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Multiphase capacitor-diode voltage multiplier
1978 IEEE Power Electronics Specialists Conference, 1978An N-phase by M-stage capacitor-diode voltage multiplier (CDVM) is described. The multiplier is failure tolerant and suitable for medium power applications. Total capacitor weight is significantly less than single-phase multipliers. Excellent correlation between test data and predicted values for output voltage, peak currents, and efficiency ...
R. M. Martinelli, A. F. Ahrens
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CMOS voltage-mode analog multiplier
2006 IEEE International Symposium on Circuits and Systems, 2006This paper proposes a CMOS voltage-mode four-quadrant analog multiplier. It is based on a pair of diode-connected MOS transistor that is biased with a constant current source, and a CMOS voltage difference circuit. Simulation results shows that the linear range is /spl plusmn/400 mV with the linearity error of 0.8% and the harmonic distortion of 0.62%.
B. Boonchu, W. Surakampontorn
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