Results 231 to 240 of about 225,334 (264)
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Determination of the stress level for voltage screen of integrated circuits
Microelectronics Reliability, 2010Abstract Voltage screen is a method to screen out products that suffer from defectivity related issues. A risk associated with voltage screen is that the applied voltage is too severe and damages the product. Most papers dealing with voltage screen determine the stress voltage by a general rule of thumb (focusing on one specific mechanism) without ...
Ramun M. Kho +6 more
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Probabilistic analysis of voltage bands stressed by electric mobility
2011 2nd IEEE PES International Conference and Exhibition on Innovative Smart Grid Technologies, 2011This contribution proposes a method to analyze the capabilities of low voltage grids to meet the demands of additional loads due to electric mobility. Probabilistic load models for both the domestic and electric vehicle loads are developed to give insight into the stochastic nature of load distribution and voltage bands.
Alexander C. Probst +3 more
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Predicting voltage stress effects on MV/LV components
2003 IEEE Bologna Power Tech Conference Proceedings,, 2004The problem of predicting voltage stress effects on MV/LV components is discussed. Reference is made to the measurement techniques of the voltage peak, which is the main cause of aging of solid type insulation, in terms of input data, aggregation intervals, observation period and statistical treatment.
GALLO, Daniele +2 more
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Lipid Stress at Play: Mechanosensitivity of Voltage-Gated Channels
2007Membrane stretch modulates the activity of voltage-gated channels (VGCs). These channels are nearly ubiquitous among eukaryotes and they are present, too, in prokaryotes, so the potential ramifications of VGC mechanosensitivity are diverse. In situ traumatic stretch can irreversibly alter VGC activity with lethal results but that is pathology.
Catherine E, Morris, Peter F, Juranka
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Eurocon 2013, 2013
The present paper aims to the investigation of the methods used to minimize or maximize the values of the Corona onset and Breakdown voltage in small rod-plate air gaps when stressed by dc or impulse voltages. The main factors which influence greatly the distribution of the electric field in the gap, and hence the above values are the geometry and the ...
Athanasios Maglaras +4 more
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The present paper aims to the investigation of the methods used to minimize or maximize the values of the Corona onset and Breakdown voltage in small rod-plate air gaps when stressed by dc or impulse voltages. The main factors which influence greatly the distribution of the electric field in the gap, and hence the above values are the geometry and the ...
Athanasios Maglaras +4 more
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27.12 MHz large voltage gain resonant converter with low voltage stress
2013 IEEE Energy Conversion Congress and Exposition, 2013This paper presents the design and implementation of a high frequency switching power converter with a large voltage gain and air core inductors. Specifically, we demonstrate a 40 W, 30 V to 300 V dc-dc converter switching at 27.12 MHz. Operating at this frequency reduces bulk energy storage over conventional low frequency designs and allows for fast ...
Luke Raymond +3 more
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Insulation Tester for Medium Voltage Components Subject to PWM Voltage Stress
2023 IEEE Electric Ship Technologies Symposium (ESTS), 2023Jesse Leonard +3 more
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Analysis and modulation of the buck-boost voltage source inverter (BBVSI) for lower voltage stresses
2015 IEEE International Conference on Industrial Technology (ICIT), 2015Renewable energy sources entail the power electronics inverters are the orbit of research objectives for optimum operation. Two commonly used inverters exist; the current source inverters (CSI) and the voltage source inverters (VSI). The first one supports only the boost capability and the other supports the buck capability, but due to the high ...
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A Grid‐Tied Voltage Boosting Multilevel Inverter With Reduced Voltage Stress and Part Count
International Journal of Circuit Theory and ApplicationsABSTRACT This paper presents a single‐phase switched‐capacitor (SC)‐based boost inverter topology capable of synthesizing a seven‐level (7L) output using only nine power switches, two capacitors, and a single DC input source. The proposed topology (PT) achieves a voltage gain of 1.5 while ensuring inherent capacitor voltage self ...
Kasinath Jena +4 more
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Microelectronics Reliability, 2007
Abstract This paper investigates the effect of NFET (N+ poly gate, N+ diffusion of FET) stress voltage conditions, for ultra-thin gate oxides, on the voltage acceleration, and lifetime projections to use conditions. This work employs the model relating the critical defect density (NBD) to the charge-to-breakdown and the defect generation probability (
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Abstract This paper investigates the effect of NFET (N+ poly gate, N+ diffusion of FET) stress voltage conditions, for ultra-thin gate oxides, on the voltage acceleration, and lifetime projections to use conditions. This work employs the model relating the critical defect density (NBD) to the charge-to-breakdown and the defect generation probability (
openaire +2 more sources