Results 161 to 170 of about 436,378 (230)

Growth of 2D Materials at the Wafer Scale

Advances in Materials, 2021
Wafer‐scale growth has become a critical bottleneck for scaling up applications of van der Waal (vdW) layered 2D materials in high‐end electronics and optoelectronics.
Xiangming Xu, Tianchao Guo, Hyunho Kim, M. K. Hota, Rajeh S Alsaadi, M. Lanza, Xi-xiang Zhang, H. Alshareef   +7 more
semanticscholar   +1 more source

Reverse Wafer Procedure

Journal of Wrist Surgery, 2023
Abstract Purpose This study aimed to present the results of an alternative technique for treating ulnar impaction syndrome, the “reverse wafer procedure,” and assess the mid-term clinical outcomes of patients treated with this technique. Methods A retrospective evaluation was conducted on 14 patients who underwent the reverse wafer ...
Ismail Bulent Ozcelik, Ali Cavit, Aydin Yuceturk   +2 more
openaire   +2 more sources

Synthesis of Wafer‐Scale Graphene with Chemical Vapor Deposition for Electronic Device Applications

Advanced Materials & Technologies, 2021
The first isolation of graphene opens the avenue for new platforms for physics, electronic engineering, and materials sciences. Among several kinds of synthesis approaches, chemical vapor deposition is most promising for the growth at wafer‐scale, which ...
Bao-min Sun, Jinbo Pang, Qilin Cheng, Shu Zhang, Yufen Li, Congcong Zhang, Dehui Sun, B. Ibarlucea, Yang-qiu Li, Duo Chen, Huaimin Fan, Qingfang Han, Meng Chao, Hong Liu, Jingang Wang, G. Cuniberti, Lin Han, Weijia Zhou   +17 more
semanticscholar   +1 more source

An Innovative Chip-to-Wafer and Wafer-to-Wafer Stacking

56th Electronic Components and Technology Conference 2006, 2006
Abundant three-dimensional packaging technologies were developed for chip-to-wafer or wafer-to-wafer bonding, which employed through silicon interconnect to achieve the shortest circuit design of inter-chip or inter-wafer. In this paper, we focused on the wafer stacking technology by introducing silicon-through three-dimensional interconnect.
null Wei-Chung Lo, null Yu-Hua Chen, null Jeng-Dar Ko, null Tzu-Ying Kuo, null Ying-Ching Shih, null Su-Tsai Lu   +5 more
openaire   +1 more source

Wafer-scale Highly Oriented Monolayer MoS2 with Large Domain Sizes.

Nano letters (Print), 2020
Two-dimensional molybdenum disulfide (MoS2) is an emergent semiconductor with great potentials in next-generation scaled-up electronics, but the production of high-quality monolayer MoS2 wafers still remains a challenge.
Qinqin Wang, Na Li, Jian Tang, Jianqi Zhu, Qinghua Zhang, Qi Jia, Ying Lu, Zheng Wei, Hua Yu, Yanchong Zhao, Yutuo Guo, Lin Gu, Gang Sun, Wei Yang, Rong Yang, D. Shi, Guangyu Zhang   +16 more
semanticscholar   +1 more source

Deformable Convolutional Networks for Efficient Mixed-Type Wafer Defect Pattern Recognition

IEEE transactions on semiconductor manufacturing, 2020
Defect pattern recognition (DPR) of wafer maps is critical for determining the root cause of production defects, which can provide insights for the yield improvement in wafer foundries.
Junliang Wang, Chuqiao Xu, Zhengliang Yang, Jie Zhang, Xiaoou Li   +4 more
semanticscholar   +1 more source

Nondestructive silicon wafer recovery by a novel method of solvothermal swelling coupled with thermal decomposition

Chemical Engineering Journal, 2021
End-of-life (EoL) photovoltaic (PV) waste is becoming a severe environmental issue worldwide. Developing technologies to reclaim nondestructive and reusable silicon wafers (Si-wafers) is the most appealing way to solve this problem, saving ∼40% on PV ...
Xin-Qi Xu, Dengguo Lai, Gang Wang, Yin Wang   +3 more
semanticscholar   +1 more source

A Deep Convolutional Neural Network for Wafer Defect Identification on an Imbalanced Dataset in Semiconductor Manufacturing Processes

IEEE transactions on semiconductor manufacturing, 2020
Wafer maps contain information about various defect patterns on the wafer surface and automatic classification of these defects plays a vital role to find their root causes.
Muhammad Saqlain, Qasim Abbas, Jong Yun Lee   +2 more
semanticscholar   +1 more source

A stacking ensemble classifier with handcrafted and convolutional features for wafer map pattern classification

Computers in industry (Print), 2021
Recently, machine learning has been effectively applied in the automation of wafer map pattern classification in semiconductor manufacturing. One conventional approach is to extract handcrafted features from a wafer map and build an off-the-shelf ...
H. Kang, Seokho Kang
semanticscholar   +1 more source

Reducing Wafer Delay Time by Robot Idle Time Regulation for Single-Arm Cluster Tools

IEEE Transactions on Automation Science and Engineering, 2021
Nowadays, wafer fabrication in semiconductor manufacturing is highly dependent on cluster tools. A cluster tool is equipped with several process modules (PMs) and a wafer handling robot. When the tool is operating, generally each PM is processing a wafer,
Wenqing Xiong, Chunrong Pan, Yan Qiao, N. Wu, Mingxin Chen, Pinhui Hsieh   +5 more
semanticscholar   +1 more source