Results 171 to 180 of about 436,378 (230)

Large and Dense Organic-Inorganic Hybrid Perovskite CH3NH3PbI3 Wafer Fabricated by One-Step Reactive Direct Wafer Production with High X-ray Sensitivity.

ACS Applied Materials and Interfaces, 2020
Lead halide perovskites with good optoelectronic properties and high attenuation of high-energy radiation are great candidates for X-ray radiation detectors. Large area, dense, and thick films or wafers are a prerequisite for these applications.
Mingxin Hu, Shanshan Jia, Yucheng Liu, Jianyu Cui, Yunxia Zhang, Hang Su, Shuqing Cao, Lihong Mo, Depeng Chu, Guangtao Zhao, K. Zhao, Zhou Yang, S. Liu   +12 more
semanticscholar   +1 more source

Convolutional Neural Network for Wafer Surface Defect Classification and the Detection of Unknown Defect Class

IEEE transactions on semiconductor manufacturing, 2019
An automatic defect classification (ADC) system identifies and classifies wafer surface defects using scanning electron microscope images. By classifying defects, manufacturers can determine whether the wafer can be repaired and proceed to the next ...
S. Cheon, Hankang Lee, C. Kim, S. Lee
semanticscholar   +1 more source

Automated Wafer Analysis using Wafer Map Autocorrelation

52nd ARFTG Conference Digest, 1998
A complete wafer map contains information sufficient to discriminate certain prober errors, parametric errors, and point defect errors even without the full measured data set. Autocorrelation of the wafer map allows a simple automated analysis system to provide immediate feedback to the operator of known errors, allowing immediate retest in case of ...
openaire   +1 more source

A wafer-to-wafer alignment technique

Sensors and Actuators, 1989
Abstract A simple, inexpensive and reliable wafer-to-wafer alignment technique is presented for use in the fabrication of microsensors and microactuators. The technique provides ±5 μm alignment precision and requires no special optical or mechanical fixtures.
R.L. Smith, S.D. Collins
openaire   +1 more source

3D Process Integration – Wafer-to-Wafer and Chip-to-Wafer Bonding

MRS Proceedings, 2006
ABSTRACTMany feasibility and design studies during the last years have shown that devices based on 3D chip stacking and integration can significantly outperform traditional planar (2D) devices. Furthermore, as packaging of the devices is a major cost factor, the possibility to integrate multiple functional entities in one package offers a huge ...
Thorsten Matthias, Markus Wimplinger, Stefan Pargfrieder, Paul Lindner   +3 more
openaire   +1 more source

Novel Cu/SiCN surface topography control for 1 μm pitch hybrid wafer-to-wafer bonding

Electronic Components and Technology Conference, 2020
This paper presents our approach to hybrid bond scaling to 1μm pitch and recent demonstration results. The direct wafer stacking of two Cu/SiCN surface is realized between slightly protruding Cu nano-pad on one wafer and slightly recessed, but larger, Cu
Soon-Wook Kim, F. Fodor, N. Heylen, S. Iacovo, J. de Vos, Andy Miller, G. Beyer, E. Beyne   +7 more
semanticscholar   +1 more source

Polycarbonates as Temporary Wafer-Wafer Adhesives

ECS Meeting Abstracts, 2011
Abstract not Available.
Nathan Fritz, Sue Ann Bidstrup Allen, Paul Kohl   +2 more
openaire   +1 more source

Through-Wafer Optical Interconnects For Multi-Wafer Wafer-Scale Integrated Architectures

SPIE Proceedings, 1986
Hybrid mounting of optical components, combined perhaps with integrated optical waveguides and lenses on a large area silicon, wafer-scale integrated (WSI) electronic circuit provides one potential approach to combine advanced electronic and photonic functions.
L A. Hornak, S K. Tewksbury, M Hatamian, A Ligtenberg, B Sugla, P Franzon   +5 more
openaire   +1 more source

Ultra-thin wafer technology and applications: A review

, 2020
Ultra-thin wafers with thickness of typically less than 200 μm are important building blocks in semiconductor device manufacturing. Due to the special mechanical properties of ultra-thin wafers, the fabrication and handling of ultra-thin wafers are ...
Zihan Dong, Yuanwei Lin
semanticscholar   +1 more source

A Voting Ensemble Classifier for Wafer Map Defect Patterns Identification in Semiconductor Manufacturing

IEEE transactions on semiconductor manufacturing, 2019
A wafer map contains a graphical representation of the locations about defect pattern on the semiconductor wafer, which can provide useful information for quality engineers.
Muhammad Saqlain, Bilguun Jargalsaikhan, Jong Yun Lee   +2 more
semanticscholar   +1 more source