Results 191 to 200 of about 436,378 (230)

Epitaxial growth of wafer-scale molybdenum disulfide semiconductor single crystals on sapphire

Nature Nanotechnology, 2021
Taotao Li, Wei Guo, Liang Ma, Weisheng Li, Zhihao Yu, Zhenyang Han, Si Gao, Lei Liu, D. Fan, Zixuan Wang, Yang Yang, Weiyi Lin, Zhongzhong Luo, Xiaoqing Chen, Ning Dai, X. Tu, D. Pan, Yagang Yao, Peng Wang, Y. Nie, Jinlan Wang, Yi Shi, Xinran Wang   +22 more
semanticscholar   +1 more source

Wafer-to-Wafer Hybrid Bonding Development by Advanced Finite Element Modeling for 3-D IC Packages

IEEE Transactions on Components, Packaging, and Manufacturing Technology, 2020
This article focuses on the 3-D modeling methodology development of the wafer-to-wafer hybrid bonding (W2W-HB) annealing process. With its successful application in a 2-stack wafer-to-wafer bonding, the Cu-to-Cu bonding area is derived and compared for ...
L. Ji, F. Che, H. Ji, Hong Yu Li, M. Kawano   +4 more
semanticscholar   +1 more source

RF W-band wafer-to-wafer transition

IEEE Transactions on Microwave Theory and Techniques, 2001
Multiwafer silicon designs must provide an avenue for electrical signals to flow from wafer to wafer. For this purpose, a two-layer electrical bond is proposed to provide electrical connection between two coplanar waveguides on vertically stacked silicon wafers. Loss of approximately 0.1 dB is measured for this compact, packaged transition at W-band.
K.J. Herrick, L.P.B. Katehi
openaire   +1 more source

Classification of Mixed-Type Defect Patterns in Wafer Bin Maps Using Convolutional Neural Networks

IEEE transactions on semiconductor manufacturing, 2018
In semiconductor manufacturing, a wafer bin map (WBM) represents the results of wafer testing for dies using a binary pass or fail value. For WBMs, defective dies are often clustered into groups of local systematic defects.
Kiryong Kyeong, Heeyoung Kim
semanticscholar   +1 more source

Low temperature wafer bonding of CMOS wafers

2012 IEEE 14th Electronics Packaging Technology Conference (EPTC), 2012
The continuous need for consumer electronics miniaturization requires not only size shrinking, but also higher degree of integration. The new demands imposed wafer bonding as an attractive technology for wafer-level integration. The resulting increased complexity of the devices brings new challenges to the processing techniques.
V. Dragoi, T. Matthias, B. Rebhan, F. Huysmans   +3 more
openaire   +1 more source

Dual-coupling-guided epitaxial growth of wafer-scale single-crystal WS2 monolayer on vicinal a-plane sapphire

Nature Nanotechnology, 2021
Jinhuan Wang, Xiaozhi Xu, Ting Cheng, Lehua Gu, Ruixi Qiao, Z. Liang, Dongdong Ding, Hao Hong, Peiming Zheng, Zhibin Zhang, Zhihong Zhang, Shuai Zhang, Guoliang Cui, Chao Chang, Chen-Hung Huang, Jiajie Qi, Jing Liang, Can Liu, Yonggang Zuo, Guo-Wei Xue, Xinjie Fang, Jinpeng Tian, Muhong Wu, Yi Guo, Zhixin Yao, Q. Jiao, Lei Liu, Peng Gao, Qunyang Li, Rong Yang, Guangyu Zhang, Zhenxun Tang, Dapeng Yu, E. Wang, Jianming Lu, Yun Zhao, Shiwei Wu, F. Ding, Kaihui Liu   +38 more
semanticscholar   +1 more source

AdaBalGAN: An Improved Generative Adversarial Network With Imbalanced Learning for Wafer Defective Pattern Recognition

IEEE transactions on semiconductor manufacturing, 2019
Identification of the defective patterns of the wafer maps can provide insights for the quality control in the semiconductor wafer fabrication systems (SWFSs). In real SWFSs, the collected wafer maps are usually imbalanced from the defective types, which
Junliang Wang, Zhengliang Yang, Jie Zhang, Qihua Zhang, W. Chien   +4 more
semanticscholar   +1 more source

Wafer edge-shot algorithm for wafer scanners

SPIE Proceedings, 2002
The requirement for the higher resolution is pushing up the NA of the projection lens, so the DOF becomes shallower and the focus budget becomes tight. On the other hand, the requirement for the higher through-put is still demanding. To achieve the best throughput, the alternate scanning exposure sequence is inevitable to current wafer scanners.
Tsuneyuki Hagiwara, Masato Hamatani, Hideyuki Tashiro, Etsuya Morita, Shinichi Okita, Naoto Kondo   +5 more
openaire   +1 more source

IC-compatible silicon wafer-to-wafer bonding

Sensors and Actuators A: Physical, 1997
Abstract In this paper a fully IC-compatible silicon wafer-to-wafer fusion-bonding process is described. Before the bonding, the silicon surfaces are treated by chemicals which do not attack the electronic circuits or aluminium patterns on the silicon. The prebonding of the two silicon wafers is performed at room temperature.
A Berthold, M.J Vellekoop
openaire   +1 more source

Wafer-to-Wafer Bonding Fabrication Process-Induced Wafer Warpage

IEEE Transactions on Semiconductor Manufacturing, 2023
Wei Feng, Haruo Shimamoto, Tsuyoshi Kawagoe, Ichirou Honma, Masato Yamasaki, Fumitake Okutsu, Takatoshi Masuda, Katsuya Kikuchi   +7 more
openaire   +1 more source