Chaotic Time Delay Systems and Field Programmable Gate Array Realization

Abstract

In this paper, we show how chaotic time delay systems can be realized physically using a Field Programmable Gate Array (FPGA) platform.

There are various analog realizations of chaotic delay differential equations (DDEs) Namajunas et al. (1995), Busarino et al. (2011), and Srinivasan et al. (2010). The disadvantage with the analog realization is the number of components required for realizing the delay (example: n operational amplifiers for an n-stage delay in Busarino et al. (2011)) and the inability to synthesize some nonlinear functions using analog electronics. For example, the Ikeda chaotic DDE (Ikeda and Matsumoto, 1987) involves a sine nonlinearity and this is difficult to synthesize using analog electronics. In fact, we are not aware of any electronic realization of the Ikeda DDE.