Loading [MathJax]/extensions/TeX/ietmacros.js
Design and Implementation of a Binary Sequence Detector with Functional Verification, Synthesis, PnR and STA using open-source EDA tool | IEEE Conference Publication | IEEE Xplore

Design and Implementation of a Binary Sequence Detector with Functional Verification, Synthesis, PnR and STA using open-source EDA tool


Abstract:

The study focuses on developing a VLSI-based Binary Sequence Detector using open-source Electronic Design Automation (EDA) tools. It emphasizes the synthesis, PnR and STA...Show More

Abstract:

The study focuses on developing a VLSI-based Binary Sequence Detector using open-source Electronic Design Automation (EDA) tools. It emphasizes the synthesis, PnR and STA of the sequence detector. Key goals include designing and implementing a binary sequence detector in Verilog, incorporating functional verification, synthesis, placement and routing, and static timing analysis (STA) through open-source EDA tools. Through a thorough literature review, reversible sequential circuit construction methods using FPGAs are explored, highlighting the effectiveness of open-source tools. Diverse methodologies for high-speed sequence detectors in Verilog are examined, emphasizing flexibility, efficiency, and scalability.
Date of Conference: 23-24 August 2024
Date Added to IEEE Xplore: 10 December 2024
ISBN Information:

ISSN Information:

Conference Location: Pune, India

Contact IEEE to Subscribe

References

References is not available for this document.