In this paper we present a full analog CMOS implementation of Gallager's iterative decoding algorithm applied to a relatively simple Block Turbo Code. The aim of our work is to investigate the potentiality of this approach in the construction of the analog decoding network, with respect to those based on the forward-backward algorithm on the trellis of the constituent codes. The work describes the design issues and the post-layout simulation results of a prototype which is going to be fabricated in a 0.8 /spl mu/m CMOS technology. The prototype implements a decoder for a rate 0.4, BTC code built from (7,4) Hamming constituent codes, with a 16-bit block length, and including on-chip I/O interfaces for serial input and parallel digital output. The simulated overall power consumption at 4.8 Mbit/s information (i.e. 12 Mbit/s channel) transmission rate was 11 mW.