Integrated filters and front-end amplifiers for audio, IoT and biomedical applications require high resistance values to implement the required very large time constants. Referring to biomedical applications, front-end amplifiers for neural recording systems often rely on AC coupling with very low cut off frequencies (below 1Hz) in order to remove the DC offset of the electrodes and to properly process the neural signals [1]–​[2]. Such systems are typically designed to cover different bandwidths in the range from 1Hz to 10kHz. For example, in the case of epileptic seizure detection, band-pass filters with a bandwidth from 250Hz to 500Hz and a sharp frequency response are required to extract the signals of interest [3]–​[4].

Designers of CMOS integrated circuits typically rely on the Switched-Capacitor [5] or the pseudo-resistor [6]–​[8] approaches to implement large resistance values. However, it has to be noted that, in switched-capacitor implementations, the resistance value is tuned by varying the clock frequency thus changing also the sample rate of the system, and this can be a disadvantage in many applications. On the other hand, pseudo-resistors are typically tuned over a wide range by changing the gate-source voltage. When using this technique, the value of the equivalent resistance is very sensitive to the common mode voltage and to PVT variations and a limited linearity performance has to be expected [9].

The Switched-Resistor (S-R) approach is becoming more and more popular within the community of integrated circuits designers, because it allows implementing very high resistances whose value can be tuned over several decades by adjusting the duty cycle of the clock signal without modifying the sample rate of the system. These characteristics are very attractive to implement large time constants in integrated circuits for IoT [10]–​[11] and biomedical applications [1]–​[8] and for a wide set of very low power integrated circuits such as for example analog to digital converters [12]. The Switched-Resistor approach has been exploited in [13]–​[16] to implement tunable filters and analog front-ends for biomedical integrated circuits. The value of the duty cycle adopted in [13] and [14] is in the range of 10% to 75% whereas a much lower value is used in [15]–​[17].

In this paper we demonstrate that the conventional model adopted for the S-R is inaccurate for values of duty cycle below 1% and propose a new analytic model of S-R which is able to describe, in an accurate way, all the main parasitic effects due to the involved devices (e.g., MOS switches and polysilicon resistors). The proposed model is very accurate even for duty cycle values as low as 0.0001% and allows to properly model both grounded and floating resistors implemented by using very small duty cycles resulting in a huge resistance multiplication factor.

The paper is structured as follows. Section II reviews the basic principle of S-R approach and the conventional model. The proposed detailed model is introduced and explained in Section III referring firstly to a grounded S-R and then to a floating S-R. The implementation of a first-order active low-pass filter with a cutoff frequency tunable from 1.68Hz to 1.46kHz is presented in Section IV and used to perform a further validation of the proposed detailed model. Conclusions are finally drawn in Section V.

The scheme of the well-known S-R architecture is depicted in Fig. 1. The conventional S-R model [13]–​[17] is based on a MOSFET switch, characterized by its on resistance $R_{on}$ , in series with an ideal poly resistor $R_{p}$ . (The off-state resistance of the switch $R_{off}$ is assumed to be infinite).

FIGURE 1.

Switched-Resistor ideal circuit.

Show All

A duty cycle controlled clock is applied to the MOSFET gate to set the average current that flows in the series. The assumptions of this model lead to neglect the current in the off-state of the switch and therefore the average current depends only on the current that flows during the on-state of the switch:

View Source\begin{equation*} I_{avg}=\frac {1}{T_{s}}\int ^{\delta Ts}_{0}{\frac {V1-V2}{R_{p}+R_{on}}~dt=}\delta \frac {V1-V2}{R_{p}+R_{on}~}\tag{1}\end{equation*}

$$\begin{equation*} R_{eq}=\frac {R_{p}+R_{on}}{\delta }\tag{2}\end{equation*}$$ View Source\begin{equation*} R_{eq}=\frac {R_{p}+R_{on}}{\delta }\tag{2}\end{equation*}

It is evident from the above equations that the conventional model completely neglects the parasitic current flowing through the TG switch in the off-state, the currents flowing through the parasitic capacitances and the current flowing in the bulk terminals of the devices implementing the TG switch. Furthermore, this model assumes that in the on-state all the current flows through the switch and the resistor, so that the current entering at node 1 is equal to the current exiting from node 2 and therefore it can be enough accurate only when the average current flowing through the resistor is much larger than the sum of all the parasitic currents.

In order to quantitatively test the accuracy of the conventional S-R model, we have implemented a switched-resistor referring to a commercial 130nm CMOS technology. In particular we have implemented a 500k$\Omega$ , high resistivity poly (hipo) resistor, taken from the technology library, followed by a transmission gate (TG) acting as switch (Wn/Ln = 150nm/130nm and Wp/Lp = 150nm/130nm) implemented with the low leakage PMOS and NMOS devices.

Periodic steady state (PSS) and periodic AC (PAC) simulations within the Cadence Virtuoso™ environment have been exploited to estimate the equivalent resistance (and therefore the equivalent conductance) as a function of the duty cycle $\delta$ .

In order to estimate the rise and fall times ($T_{rise}$ and $T_{fall}$ respectively) of realistic clock waveforms, we have carried out some simulations in which the CMOS NOT gates taken from the digital library of the 130nm technology have been used to drive the clock inputs of the TG switches adopted in our S-R implementations. The rise and fall times have been found lower than 30ps, and according to this result we have chosen a clock frequency of 10kHz and pushed the duty cycle down to 0.0001% in order to have a $T_{on}=\delta *T_{ck}\,\,=\,\,100$ ps > ($T_{rise}+ T_{fall}$ ).

The simulation setup and the tolerance settings of PSS and PAC simulations have been carefully analyzed and verified against several examples with fully known behavior. We have found that a simulation setting parameter which is very important for the simulation accuracy is the number of harmonics in the PSS simulation. In fact, since the clock of the S-R is a square wave with steep edges, a very high number of harmonics of the clock fundamental frequency is required to fully describe the commutations of the TG switch. Extensive simulation analysis allowed us to set the number of harmonics to 60000 which resulted in sufficient simulation accuracy for all the considered duty cycle values.

The equivalent conductance of the S-R predicted by the conventional model in equation (2) and by means of the PSS+PAC simulations are reported in Fig. 2a, whereas the relative error of the model with respect to simulations is shown in Fig. 2b. By looking at Fig. 2, it is evident that the accuracy of the model in (2) starts to decrease when the duty cycle is reduced below 1%. This fact demonstrates that the conventional model is not adequate to represent the behaviour of the S-R for low duty cycles.

FIGURE 2.

Switched-Resistor conventional model: (a) comparison with the experimental Switched-Resistor; (b) relative error of the conventional model with respect to the simulated Switched-Resistor.

Show All

This strongly limits the usability of the conventional model for high resistance multiplication factors which are very important for most applications. As it will be better shown in the following, the large relative error obtained in Fig. 2b for low duty cycles can be explained by two main parasitic effects which are not taken into account:

1. the parasitic current loss in the parasitic capacitances of both the poly resistor and the MOS switches;

2. the current flowing in the off-state, due to the finite value of the off-state resistance $R_{off}$ of the MOS switches.

A more detailed and accurate model of the S-R can be obtained by accounting also for parasitic capacitances and off-state resistances as shown in Fig. 3. In Fig. 3, the polysilicon resistor is represented by its resistance $R_{p}$ and two parasitic capacitances $C_{p1,2}$ whose value is dependent on $R_{p}$ [18]. The TG MOS switch is characterized by the parasitic resistances $R_{on}/R_{off}$ which denote its on/off-state equivalent resistances and by two parasitic capacitances $C_{TG1,2}$ .

FIGURE 3.

Proposed detailed model of the Switched-Resistor.

Show All

We have computed the values of the parameters of the model in Fig. 3 for the S-R implemented in the 130nm CMOS technology and adopted in Section II to quantify the accuracy of the conventional model.

From the simulations we have seen that the TG switch provides parasitic capacitances $C_{TG1,2}$ in the range of 0.1fF, whereas the $500 k{\Omega }$ , hipo resistor exhibits parasitic capacitance $C_{p1,2}$ of about 45.1fF. Finally, the parasitic resistances $R_{on}/R_{off}$ of the TG switches have been computed as $7.34k{\Omega }/166G{\Omega }$ respectively.

It is evident from Fig. 3 that the current flowing into the terminal $V_{1}$ of the S-R will be different from the current flowing out of the terminal $V_{2}$ . In the general case, the S-R has thus to be modeled not as a bipole but as a 2-port network. We will initially consider the case of a grounded resistor (i.e., $V_{2}$ = 0) to illustrate the development of the model, and will then develop the complete model of the floating resistor.

A. Modeling a Grounded Switched-Resistor

In this subsection we start with the model of a grounded S-R, where $V_{2}$ is grounded and $V_{1}$ is given by the signal voltage $V_{sig}$ . In the following analysis, we assume a constant $V_{sig}$ and therefore we neglect the capacitor $C_{TG\mathrm {1}}$ , in parallel to $V_{1}$ . However the effect of $C_{TG\mathrm {1}}$ can be always added in parallel to the S-R model that we are going to derive.

Being the S-R a switched system, the average current is determined considering the two equivalent circuits corresponding to the on- and off-state of the switch as shown in Fig. 3. In our approach we determine for each state the voltage $V_{c}$ in the “s” domain as follows:

$$\begin{equation*} V_{c_{on}}=V_{sig}\left ({s}\right)\frac {R_{p}}{R_{p}+R_{on}}~*\frac {1}{1+s{\tau }_{on}}\tag{3}\end{equation*}$$ View Source\begin{equation*} V_{c_{on}}=V_{sig}\left ({s}\right)\frac {R_{p}}{R_{p}+R_{on}}~*\frac {1}{1+s{\tau }_{on}}\tag{3}\end{equation*} where $\,\,{\tau }_{on}=(C_{p1}+C_{TG2})(R_{on}\mathrm {//}R_{p})$ $$\begin{equation*} V_{c_{off}}=V_{sig}\left ({s}\right)\frac {R_{p}}{R_{p}+R_{off}} *\frac {1}{\mathrm {1+}s{\tau }_{off}}\tag{4}\end{equation*}$$ View Source\begin{equation*} V_{c_{off}}=V_{sig}\left ({s}\right)\frac {R_{p}}{R_{p}+R_{off}} *\frac {1}{\mathrm {1+}s{\tau }_{off}}\tag{4}\end{equation*} where ${\tau }_{off}\,\,=\,\,\left ({C_{p1}+C_{TG2}}\right)(R_{off}\mathrm {//}R_{p})$

Since we are assuming a constant signal $V_{sig}\,\,=\,\,V_{s}$ and an ideal clock, we can exploit the Laplace inverse transform to obtain the time domain expressions:

$$\begin{align*} & \quad V_{c_{on}}\left ({t}\right)=V_{s}~{\alpha }_{on}~\left ({1-e^{-\,\,\frac {t}{\tau _{on}}}}\right)+{\mathrm {V}}_{\mathrm {c}}\left ({0}\right){\mathrm {e}}^{-\frac {\mathrm {t}}{~\tau _{\mathrm {on}}}}\tag{5}\\ &V_{c_{off}}\left ({t}\right)=V_{s}~{\alpha }_{off}\left ({1-e^{-\,\,\frac {t}{\tau _{off}}}}\right)+{\mathrm {V}}_{\mathrm {c}}\left ({\delta {\mathrm {T}}_{\mathrm {ck}}}\right){\mathrm {e}}^{-\frac {\mathrm {t}}{~\tau _{\mathrm {off}}}}\tag{6}\end{align*}$$ View Source\begin{align*} & \quad V_{c_{on}}\left ({t}\right)=V_{s}~{\alpha }_{on}~\left ({1-e^{-\,\,\frac {t}{\tau _{on}}}}\right)+{\mathrm {V}}_{\mathrm {c}}\left ({0}\right){\mathrm {e}}^{-\frac {\mathrm {t}}{~\tau _{\mathrm {on}}}}\tag{5}\\ &V_{c_{off}}\left ({t}\right)=V_{s}~{\alpha }_{off}\left ({1-e^{-\,\,\frac {t}{\tau _{off}}}}\right)+{\mathrm {V}}_{\mathrm {c}}\left ({\delta {\mathrm {T}}_{\mathrm {ck}}}\right){\mathrm {e}}^{-\frac {\mathrm {t}}{~\tau _{\mathrm {off}}}}\tag{6}\end{align*} where ${\alpha }_{on}\,\,=\,\,\frac {R_{p}}{R_{p}+R_{on}};\,\,{\alpha }_{off}=\,\,\frac {R_{p}}{R_{p}+R_{off}}$ .

Furthermore, since the initial voltage on the parasitic capacitances is unknown, the initial conditions are necessary to describe the phenomena that depend on the previous cycle states. At this purpose we set the following conditions:

$$\begin{align*} \begin{cases} V_{c_{on}}\left ({0}\right)=V_{c_{off}}(T_{ck}) \\ V_{c_{on}}\left ({\delta T_{ck}}\right)=V_{c_{off}}\left ({\delta T_{ck}}\right) \end{cases}\tag{7}\end{align*}$$ View Source\begin{align*} \begin{cases} V_{c_{on}}\left ({0}\right)=V_{c_{off}}(T_{ck}) \\ V_{c_{on}}\left ({\delta T_{ck}}\right)=V_{c_{off}}\left ({\delta T_{ck}}\right) \end{cases}\tag{7}\end{align*} After solving the system in (7) we can derive the initial conditions as follows: $$\begin{align*} V_{c}\left ({0}\right)=&V_{s}\left [{\!\!\frac {\alpha _{off}\left ({1\!-\!e^{\!-\!\frac {\left ({1\!-\!\delta }\right)T_{ck}}{\tau _{off~}}}}\right)\!+\!{\alpha }_{on}\left ({1\!-\!e^{\!-\!~\frac {\delta T_{ck}}{\tau _{on}~}}}\right)e^{\!-\!\frac {\left ({1\!-\!\delta }\right)T_{ck}}{\tau _{off~}}}}{\left ({1\!-\!e^{\!-\!~\frac {\delta T_{ck}}{\tau _{on~}}}*e^{\!-\!~\frac {\left ({1\!-\!\delta }\right)T_{ck}}{\tau _{off~}}}}\right)}\!\!}\right]\tag{8}\\ V_{c}\left ({\delta T_{ck}}\right)=&V_{s}\Biggl [{\vphantom {\frac {\alpha _{off}\left ({1-e^{-\frac {\left ({1-\delta }\right)T_{ck}}{\tau _{off~}}}}\right)+{\alpha }_{on}\left ({1-e^{-\,\,\frac {\delta T_{ck}}{\tau _{on}~}}}\right)e^{-\frac {\left ({1-\delta }\right)T_{ck}}{\tau _{off~}}}}{\left ({1-e^{-\,\,\frac {\delta T_{ck}}{\tau _{on~}}}*e^{-\,\,\frac {\left ({1-\delta }\right)T_{ck}}{\tau _{off~}}}}\right)}}{\alpha }_{on}\left ({1-e^{-\,\,\frac {\delta T_{ck}}{\tau _{on}~}}}\right)} \\&\quad +\,\,\frac {\alpha _{off}\left ({1-e^{-\frac {\left ({1-\delta }\right)T_{ck}}{\tau _{off~}}}}\right)+{\alpha }_{on}\left ({1-e^{-\,\,\frac {\delta T_{ck}}{\tau _{on}~}}}\right)e^{-\frac {\left ({1-\delta }\right)T_{ck}}{\tau _{off~}}}}{\left ({1-e^{-\,\,\frac {\delta T_{ck}}{\tau _{on~}}}*e^{-\,\,\frac {\left ({1-\delta }\right)T_{ck}}{\tau _{off~}}}}\right)} \\&\qquad {*~{\mathrm {e}}^{-\frac {\delta {\mathrm {T}}_{\mathrm {ck}}}{\tau _{\mathrm {on}}}}\vphantom {\frac {\alpha _{off}\left ({1-e^{-\frac {\left ({1-\delta }\right)T_{ck}}{\tau _{off~}}}}\right)+{\alpha }_{on}\left ({1-e^{-\,\,\frac {\delta T_{ck}}{\tau _{on}~}}}\right)e^{-\frac {\left ({1-\delta }\right)T_{ck}}{\tau _{off~}}}}{\left ({1-e^{-\,\,\frac {\delta T_{ck}}{\tau _{on~}}}*e^{-\,\,\frac {\left ({1-\delta }\right)T_{ck}}{\tau _{off~}}}}\right)}}}\Biggr] \\ {}\tag{9}\end{align*}$$ View Source\begin{align*} V_{c}\left ({0}\right)=&V_{s}\left [{\!\!\frac {\alpha _{off}\left ({1\!-\!e^{\!-\!\frac {\left ({1\!-\!\delta }\right)T_{ck}}{\tau _{off~}}}}\right)\!+\!{\alpha }_{on}\left ({1\!-\!e^{\!-\!~\frac {\delta T_{ck}}{\tau _{on}~}}}\right)e^{\!-\!\frac {\left ({1\!-\!\delta }\right)T_{ck}}{\tau _{off~}}}}{\left ({1\!-\!e^{\!-\!~\frac {\delta T_{ck}}{\tau _{on~}}}*e^{\!-\!~\frac {\left ({1\!-\!\delta }\right)T_{ck}}{\tau _{off~}}}}\right)}\!\!}\right]\tag{8}\\ V_{c}\left ({\delta T_{ck}}\right)=&V_{s}\Biggl [{\vphantom {\frac {\alpha _{off}\left ({1-e^{-\frac {\left ({1-\delta }\right)T_{ck}}{\tau _{off~}}}}\right)+{\alpha }_{on}\left ({1-e^{-\,\,\frac {\delta T_{ck}}{\tau _{on}~}}}\right)e^{-\frac {\left ({1-\delta }\right)T_{ck}}{\tau _{off~}}}}{\left ({1-e^{-\,\,\frac {\delta T_{ck}}{\tau _{on~}}}*e^{-\,\,\frac {\left ({1-\delta }\right)T_{ck}}{\tau _{off~}}}}\right)}}{\alpha }_{on}\left ({1-e^{-\,\,\frac {\delta T_{ck}}{\tau _{on}~}}}\right)} \\&\quad +\,\,\frac {\alpha _{off}\left ({1-e^{-\frac {\left ({1-\delta }\right)T_{ck}}{\tau _{off~}}}}\right)+{\alpha }_{on}\left ({1-e^{-\,\,\frac {\delta T_{ck}}{\tau _{on}~}}}\right)e^{-\frac {\left ({1-\delta }\right)T_{ck}}{\tau _{off~}}}}{\left ({1-e^{-\,\,\frac {\delta T_{ck}}{\tau _{on~}}}*e^{-\,\,\frac {\left ({1-\delta }\right)T_{ck}}{\tau _{off~}}}}\right)} \\&\qquad {*~{\mathrm {e}}^{-\frac {\delta {\mathrm {T}}_{\mathrm {ck}}}{\tau _{\mathrm {on}}}}\vphantom {\frac {\alpha _{off}\left ({1-e^{-\frac {\left ({1-\delta }\right)T_{ck}}{\tau _{off~}}}}\right)+{\alpha }_{on}\left ({1-e^{-\,\,\frac {\delta T_{ck}}{\tau _{on}~}}}\right)e^{-\frac {\left ({1-\delta }\right)T_{ck}}{\tau _{off~}}}}{\left ({1-e^{-\,\,\frac {\delta T_{ck}}{\tau _{on~}}}*e^{-\,\,\frac {\left ({1-\delta }\right)T_{ck}}{\tau _{off~}}}}\right)}}}\Biggr] \\ {}\tag{9}\end{align*}

Then we can determine the expression of the equivalent resistor ($R_{S-R})$ by computing the average current that flows in $R_{p}$ and $C_{p}\,\,=\,\,\left ({C_{p1}+C_{TG2}}\right)$ in a clock period:

$$\begin{align*} I_{avg}=&\frac {1}{T_{ck}}\Biggl [{\int ^{\delta Tck~}_{0}\left ({C_{p}\frac {dV_{c_{on}}(t)}{dt}+\frac {V_{c_{on}}\left ({t}\right)}{R_{p}} }\right)dt} \\&{\quad +\,\,\int ^{T_{ck}~}_{\delta T_{ck}}\left ({C_{p}\frac {dV_{c_{off}}\left ({t}\right)}{dt}\,\,+\frac {V_{c_{off}}\left ({t}\right)}{R_{p}}~}\right)~dt~}\Biggr]\tag{10}\end{align*}$$ View Source\begin{align*} I_{avg}=&\frac {1}{T_{ck}}\Biggl [{\int ^{\delta Tck~}_{0}\left ({C_{p}\frac {dV_{c_{on}}(t)}{dt}+\frac {V_{c_{on}}\left ({t}\right)}{R_{p}} }\right)dt} \\&{\quad +\,\,\int ^{T_{ck}~}_{\delta T_{ck}}\left ({C_{p}\frac {dV_{c_{off}}\left ({t}\right)}{dt}\,\,+\frac {V_{c_{off}}\left ({t}\right)}{R_{p}}~}\right)~dt~}\Biggr]\tag{10}\end{align*} Since the average current in (10) is the sum of two contributions (the first referred to the on state and the second to the off -state), the equivalent resistance can be calculated as two resistances in parallel, the first ($R_{S-R_{on}})$ is related to the current flowing when the switch is close, whereas the second $R_{S-R_{off}}$ is related to the small current flowing when the switch is open: $$\begin{align*} R_{S-R}=&\frac {V_{s}}{I_{avg}}=R_{SR_{on}}//R_{SR_{off}}\tag{11}\\ R_{S-R_{on}}=&\frac {R_{p}}{\delta {~\alpha }_{on}+\,\,F_{ck}\left [{\left ({{\tau }_{on}-C_{p}R_{p}~}\right)\left ({~{V_{an}}_{c}\left ({0}\right)-{\alpha }_{on}}\right)}\right]\left ({\!1-e^{-\frac {\delta T_{ck}}{\tau _{on}}}\!}\right)}\tag{12}\\&R_{S-R_{off}} \\=&\frac {R_{p}}{\left ({1-\delta }\right){~\alpha }_{off}+F_{ck}\left [{\left ({{\tau }_{off}-C_{p}R_{p}~}\right)\left ({~{V_{an}}_{c}\left ({\delta T_{ck}}\right)-{\alpha }_{off}}\right)}\right]\left ({\!1\!-\!e^{-\frac {(\!1-\delta \!)T_{ck}}{\tau _{off}}}\!}\right)}, \\ \tag{13}\end{align*}$$ View Source\begin{align*} R_{S-R}=&\frac {V_{s}}{I_{avg}}=R_{SR_{on}}//R_{SR_{off}}\tag{11}\\ R_{S-R_{on}}=&\frac {R_{p}}{\delta {~\alpha }_{on}+\,\,F_{ck}\left [{\left ({{\tau }_{on}-C_{p}R_{p}~}\right)\left ({~{V_{an}}_{c}\left ({0}\right)-{\alpha }_{on}}\right)}\right]\left ({\!1-e^{-\frac {\delta T_{ck}}{\tau _{on}}}\!}\right)}\tag{12}\\&R_{S-R_{off}} \\=&\frac {R_{p}}{\left ({1-\delta }\right){~\alpha }_{off}+F_{ck}\left [{\left ({{\tau }_{off}-C_{p}R_{p}~}\right)\left ({~{V_{an}}_{c}\left ({\delta T_{ck}}\right)-{\alpha }_{off}}\right)}\right]\left ({\!1\!-\!e^{-\frac {(\!1-\delta \!)T_{ck}}{\tau _{off}}}\!}\right)}, \\ \tag{13}\end{align*} where ${V_{an}}_{c}\left ({0}\right)$ = $\frac {V_{c}\left ({0}\right)}{V_{s}}\,\,{\mathrm{ and}}\,\,{\,\,V_{an}}_{c}\left ({\delta T_{ck}}\right)= \frac {V_{c}\left ({\delta T_{ck}}\right)}{V_{s}}$ .

In order to quantitatively test the accuracy of the proposed detailed S-R model we have considered the same S-R used to test the validity of the standard model (thus the simulated curve in Fig. 4a is the same than in Fig. 2a) and we have compared the results of PSS+PAC simulations with respect to the conductance ${\left ({R_{S-R}}\right)}^{-1}$ , computed from (11). The simulation parameters are the same adopted in Section II. The results of this comparison are reported in Fig. 4a to show how the detailed model fits very well with the behavior of the simulated Switched-Resistor. Fig. 4b reports the relative error of the detailed model which results lower than 2% even for duty cycle values as low as 0.0001%.

FIGURE 4.

Proposed Switched-Resistor detailed model: (a) comparison between PSS+PAC simulations and conventional model; (b) relative error of the proposed detailed model against PSS+PAC simulations.

Show All

A comparison of the proposed model against the conventional one shows how it is able to reproduce the simulated curve even when it starts differing from the linear behaviour.

In particular, by looking at the detailed model in Fig. 3 it can be understood that, due to the parasitic capacitance $C_{p1}$ , a part of the current flowing through the TG is steered toward ground so that the current flowing through the resistor $R_{p}$ is scaled by a factor $\left({1-e^{-\,\,\frac {\delta T_{ck}}{\tau _{on}\,\,}}}\right)$ .

This effect becomes dominant when the duty cycle decreases and explains the behaviour of the conductance curve in Fig. 2a.

B. Floating Switched-Resistor

In this subsection we consider the model of the generic floating S-R. As stated in the previous subsection, in the general case, the S-R has to be modeled as a 2-port network to take into account the difference of the currents at the two terminals.

The 2-port network can be described by means of different kinds of parameters and we adopt the Y parameters to develop our model. The choice of the Y-matrix allows to easily include the capacitances in parallel to port 1 and port 2 of the network (e.g., $C_{TG1}$ and $C_{p2}$ in Fig. 3) after having developed the model of the internal part of the circuit (see Fig. 5).

FIGURE 5.

Y-parameters model of the floating Switched-Resistor.

Show All

The parameters of the Y-matrix can be written as follows:

$$\begin{align*} Y11=&{\left.{\frac {I_{1}}{V_{1}}}\right |}_{V_{2}=0}=Y{11}_{on}+Y{11}_{off}\tag{14}\\ Y21=&{\left.{\frac {I_{2}}{V_{1}}}\right |}_{V_{2}=0}=Y{21}_{on}+Y{21}_{off}\tag{15}\\ Y12=&{\left.{\frac {I_{1}}{V_{2}}}\right |}_{V_{1}=0}=Y{21}_{on}+Y{21}_{off}\tag{16}\\ Y22=&{\left.{\frac {I_{2}}{V_{2}}}\right |}_{V_{1}=0}=Y{22}_{on}+Y{22}_{off}\tag{17}\end{align*}$$ View Source\begin{align*} Y11=&{\left.{\frac {I_{1}}{V_{1}}}\right |}_{V_{2}=0}=Y{11}_{on}+Y{11}_{off}\tag{14}\\ Y21=&{\left.{\frac {I_{2}}{V_{1}}}\right |}_{V_{2}=0}=Y{21}_{on}+Y{21}_{off}\tag{15}\\ Y12=&{\left.{\frac {I_{1}}{V_{2}}}\right |}_{V_{1}=0}=Y{21}_{on}+Y{21}_{off}\tag{16}\\ Y22=&{\left.{\frac {I_{2}}{V_{2}}}\right |}_{V_{1}=0}=Y{22}_{on}+Y{22}_{off}\tag{17}\end{align*} The Y11 parameter has been already calculated in the previous subsection (Grounded S-R model) and is equal to ${1}/{R_{S-R}}$ , whereas the other parameters can be computed in a similar manner, according to their definition, as shown below: $$\begin{align*} Y{21}_{on}=&- \frac {\delta {~\alpha }_{on}+{[F}_{ck}{\tau }_{on} ({V_{an}}_{c}\left ({0}\right)-{\alpha }_{on})]\left ({1-e^{-\frac {\delta T_{ck}}{\tau _{on}}}}\right)}{R_{p}}\tag{18}\\ Y{21}_{off}=&-\frac {\left ({1-\delta }\right){\alpha }_{off}+{[F}_{ck}{\tau }_{off}({V_{n}}_{c}\left ({\delta T_{ck}}\right)-{\alpha }_{off})]\left ({1-e^{-\frac {(1-\delta)T_{ck}}{\tau _{off}}}}\right)}{R_{p}}\tag{19}\\ Y{22}_{on}=&\frac {\delta {\beta }_{on}+\,\,F_{ck}[({\tau }_{on}-C_{p}R_{on})({V_{bn}}_{c}\left ({0}\right)-{\beta }_{on})]\left ({1-e^{-\frac {\delta T_{ck}}{\tau _{on}}}}\right)}{R_{on}}\tag{20}\\ Y{22}_{off}=&\frac {\left ({1-\delta }\right){\beta }_{off}+F_{ck}[({\tau }_{off}-{C_{p}R}_{off})({V_{bn}}_{c}\left ({\delta T_{ck}}\right)-{\beta }_{off})]\left ({1-e^{-\frac {(1-\delta)T_{ck}}{\tau _{off}}}}\right)}{R_{off}} \\ \tag{21}\\ Y{12}_{on}=&- \frac {\delta {\beta }_{on}+{[F}_{ck}{\tau }_{on} ({V_{bn}}_{c}\left ({0}\right)-{\beta }_{on})]\left ({1-e^{-\frac {\delta T_{ck}}{\tau _{on}}}}\right)}{R_{on}}\tag{22}\\ Y{12}_{off}=&-\frac {\left ({1-\delta }\right){\beta }_{off}+{[F}_{ck}{\tau }_{off}({V_{bn}}_{c}\left ({\delta T_{ck}}\right)-{\beta }_{off})]\left ({1-e^{-\frac {(1-\delta)T_{ck}}{\tau _{off}}}}\right)}{R_{off}}\tag{23}\end{align*}$$ View Source\begin{align*} Y{21}_{on}=&- \frac {\delta {~\alpha }_{on}+{[F}_{ck}{\tau }_{on} ({V_{an}}_{c}\left ({0}\right)-{\alpha }_{on})]\left ({1-e^{-\frac {\delta T_{ck}}{\tau _{on}}}}\right)}{R_{p}}\tag{18}\\ Y{21}_{off}=&-\frac {\left ({1-\delta }\right){\alpha }_{off}+{[F}_{ck}{\tau }_{off}({V_{n}}_{c}\left ({\delta T_{ck}}\right)-{\alpha }_{off})]\left ({1-e^{-\frac {(1-\delta)T_{ck}}{\tau _{off}}}}\right)}{R_{p}}\tag{19}\\ Y{22}_{on}=&\frac {\delta {\beta }_{on}+\,\,F_{ck}[({\tau }_{on}-C_{p}R_{on})({V_{bn}}_{c}\left ({0}\right)-{\beta }_{on})]\left ({1-e^{-\frac {\delta T_{ck}}{\tau _{on}}}}\right)}{R_{on}}\tag{20}\\ Y{22}_{off}=&\frac {\left ({1-\delta }\right){\beta }_{off}+F_{ck}[({\tau }_{off}-{C_{p}R}_{off})({V_{bn}}_{c}\left ({\delta T_{ck}}\right)-{\beta }_{off})]\left ({1-e^{-\frac {(1-\delta)T_{ck}}{\tau _{off}}}}\right)}{R_{off}} \\ \tag{21}\\ Y{12}_{on}=&- \frac {\delta {\beta }_{on}+{[F}_{ck}{\tau }_{on} ({V_{bn}}_{c}\left ({0}\right)-{\beta }_{on})]\left ({1-e^{-\frac {\delta T_{ck}}{\tau _{on}}}}\right)}{R_{on}}\tag{22}\\ Y{12}_{off}=&-\frac {\left ({1-\delta }\right){\beta }_{off}+{[F}_{ck}{\tau }_{off}({V_{bn}}_{c}\left ({\delta T_{ck}}\right)-{\beta }_{off})]\left ({1-e^{-\frac {(1-\delta)T_{ck}}{\tau _{off}}}}\right)}{R_{off}}\tag{23}\end{align*} where we define ${V_{bn}}_{c}\left ({0}\right),~{V_{bn}}_{c}\left ({\delta T_{ck}}\right)$ , ${\beta }_{on}$ , ${\beta }_{off}$ as follows: $$\begin{align*} {V_{bn}}_{c}\left ({0}\right)=&\left [{\frac {\beta _{off}\left ({1-e^{-\frac {\left ({1-\delta }\right)T_{ck}}{\tau _{off~}}}}\right)+{\beta }_{on}\left ({1-e^{-\,\,\frac {\delta T_{ck}}{\tau _{on}~}}}\right)e^{-\frac {\left ({1-\delta }\right)T_{ck}}{\tau _{off}}}}{\left ({1-e^{-\,\,\frac {\delta T_{ck}}{\tau _{on}}}*e^{-\,\,\frac {\left ({1-\delta }\right)T_{ck}}{\tau _{off}}}}\right)}}\right]\tag{24}\\ {V_{bn}}_{c}\left ({\delta T_{ck}}\right)=&\Biggl [{\vphantom {+\,\,\frac {\beta _{off}\left ({1-e^{-\frac {\left ({1-\delta }\right)T_{ck}}{\tau _{off~}}}}\right)+{\beta }_{on}\left ({1-e^{-\,\,\frac {\delta T_{ck}}{\tau _{on}~}}}\right)e^{-\frac {\left ({1-\delta }\right)T_{ck}}{\tau _{off~}}}}{\left ({1-e^{-\,\,\frac {\delta T_{ck}}{\tau _{on~}}}*e^{-\,\,\frac {\left ({1-\delta }\right)T_{ck}}{\tau _{off~}}}}\right)}{\mathrm {e}}^{-\frac {d{\mathrm {T}}_{\mathrm {ck}}}{~t_{\mathrm {on}}}}}{\beta }_{on}\left ({1-e^{-\frac {\delta T_{ck}}{\tau _{on}~}}}\right)} \\&{+\,\,\frac {\beta _{off}\left ({1-e^{-\frac {\left ({1-\delta }\right)T_{ck}}{\tau _{off~}}}}\right)+{\beta }_{on}\left ({1-e^{-\,\,\frac {\delta T_{ck}}{\tau _{on}~}}}\right)e^{-\frac {\left ({1-\delta }\right)T_{ck}}{\tau _{off~}}}}{\left ({1-e^{-\,\,\frac {\delta T_{ck}}{\tau _{on~}}}*e^{-\,\,\frac {\left ({1-\delta }\right)T_{ck}}{\tau _{off~}}}}\right)}{\mathrm {e}}^{-\frac {\delta {\mathrm {T}}_{\mathrm {ck}}}{\tau _{\mathrm {on}}}}}\Biggr] \\ \tag{25}\\ {\beta }_{on}=&\frac {R_{on}}{R_{p}+R_{on}};~{\beta }_{off}=\,\,\frac {R_{off}}{R_{p}+R_{off}}\tag{26}\end{align*}$$ View Source\begin{align*} {V_{bn}}_{c}\left ({0}\right)=&\left [{\frac {\beta _{off}\left ({1-e^{-\frac {\left ({1-\delta }\right)T_{ck}}{\tau _{off~}}}}\right)+{\beta }_{on}\left ({1-e^{-\,\,\frac {\delta T_{ck}}{\tau _{on}~}}}\right)e^{-\frac {\left ({1-\delta }\right)T_{ck}}{\tau _{off}}}}{\left ({1-e^{-\,\,\frac {\delta T_{ck}}{\tau _{on}}}*e^{-\,\,\frac {\left ({1-\delta }\right)T_{ck}}{\tau _{off}}}}\right)}}\right]\tag{24}\\ {V_{bn}}_{c}\left ({\delta T_{ck}}\right)=&\Biggl [{\vphantom {+\,\,\frac {\beta _{off}\left ({1-e^{-\frac {\left ({1-\delta }\right)T_{ck}}{\tau _{off~}}}}\right)+{\beta }_{on}\left ({1-e^{-\,\,\frac {\delta T_{ck}}{\tau _{on}~}}}\right)e^{-\frac {\left ({1-\delta }\right)T_{ck}}{\tau _{off~}}}}{\left ({1-e^{-\,\,\frac {\delta T_{ck}}{\tau _{on~}}}*e^{-\,\,\frac {\left ({1-\delta }\right)T_{ck}}{\tau _{off~}}}}\right)}{\mathrm {e}}^{-\frac {d{\mathrm {T}}_{\mathrm {ck}}}{~t_{\mathrm {on}}}}}{\beta }_{on}\left ({1-e^{-\frac {\delta T_{ck}}{\tau _{on}~}}}\right)} \\&{+\,\,\frac {\beta _{off}\left ({1-e^{-\frac {\left ({1-\delta }\right)T_{ck}}{\tau _{off~}}}}\right)+{\beta }_{on}\left ({1-e^{-\,\,\frac {\delta T_{ck}}{\tau _{on}~}}}\right)e^{-\frac {\left ({1-\delta }\right)T_{ck}}{\tau _{off~}}}}{\left ({1-e^{-\,\,\frac {\delta T_{ck}}{\tau _{on~}}}*e^{-\,\,\frac {\left ({1-\delta }\right)T_{ck}}{\tau _{off~}}}}\right)}{\mathrm {e}}^{-\frac {\delta {\mathrm {T}}_{\mathrm {ck}}}{\tau _{\mathrm {on}}}}}\Biggr] \\ \tag{25}\\ {\beta }_{on}=&\frac {R_{on}}{R_{p}+R_{on}};~{\beta }_{off}=\,\,\frac {R_{off}}{R_{p}+R_{off}}\tag{26}\end{align*}

An interesting consideration that can be done looking at the equations derived above is related to the maximum equivalent resistance that can be realized by a S-R in the limit case of zero duty cycle. In fact, if we consider $\delta \to 0$ , then ${Y_{ij}}_{off}>Y_{ij_{on}}$ and the value of the equivalent resistance is set by the off-state resistance of the switch $R_{off}$ . In other words, the average current in off-state is much larger than the average current in the on-state.

The Y-parameters curves obtained for the proposed model are compared with the simulated S-R in Fig. 6. The simulation parameters are the same used in Section II. All the Y-parameters of the model fit the simulated curves with a maximum error lower than 5.15% and an average error lower than 0.53%.

FIGURE 6.

Y-parameters validation: (a-c-e) Comparison Y-parameters with Switched-Resistor simulations and conventional model; (b-d-f) relative error of model for each Y-parameter.

Show All

It has to be noted that further parasitic effects are present in a real S-R implementation: in particular we can mention the channel charge injection and clock feedthrough effects associated with the switch [19]–​[21].

The channel charge injection is associated to the switch changing from the on- to off-state and vice versa: charge is absorbed by the switch to form the conducting channel and released when the devices enter the cutoff region, thus altering the voltage on the parasitic capacitances C_TG1 and C_TG2. The clock feedthrough is related to the edges of the clock signal that affect such parasitic capacitances through the internal capacitances of the MOS devices. Both these effects can be modeled by a voltage $\Delta$ V to be added to the initial conditions (8) and (9); however for practical implementations of the S-R their effect is negligible, resulting in an average current in the order of fA, as also shown by the good fitting of the proposed model.

As a further validation, post-layout simulations of the switched-resistor have been carried out. The two CMOS inverters driving the TG switch have been included in the layout to account for realistic clock waveforms. Post-layout simulations results show very limited variations of the Y parameters with respect to pre-layout ones, which are mainly due to the CMOS inverters and to additional parasitic capacitance of the layout. The error of the proposed accurate model with respect to post-layout simulations has been found to be below 1.5%.

C. Symmetrical Switched-Resistor

The S-R Y-model derived above does not take into account the parasitic capacitances $C_{p2}$ and $C_{TG1}$ shown in Fig. 5. Since these capacitances are in parallel with the Y11 and Y22 parameters, the Y-matrix including the parasitic capacitances can be easily derived as follows:

$$\begin{align*} Y_{S-R}=\left [{ \begin{array}{lll} Y11+sC_{TG1} & Y12~\\ Y21 & Y22+sC_{p2} \end{array} }\right]\tag{27}\end{align*}$$ View Source\begin{align*} Y_{S-R}=\left [{ \begin{array}{lll} Y11+sC_{TG1} & Y12~\\ Y21 & Y22+sC_{p2} \end{array} }\right]\tag{27}\end{align*}

It has to be noted that the Y-matrix of an ideal floating resistor is symmetrical with diagonal elements equal to each other (i.e., $Y11$ = $Y22$ and $Y12$ = $Y21$ ) and therefore these properties of the Y-matrix of a S-R are fundamental to achieve an accurate emulation of the floating resistor behavior.

By inspecting the $Y_{S-R}$ matrix in (27) it is evident that $\text{Y}11 _{\mathrm {S-R}}$ and $\text{Y}22 _{\mathrm {S-R}}$ are not equal to each other end therefore the Y $_{\mathrm {S-R}}$ matrix does not represent an ideal floating resistor.

Starting from this observation we propose a simple modification to the basic S-R topology in order to design a fully symmetric S-R. The proposed S-R topology is reported in Fig. 7, showing how an additional TG can be exploited to improve the floating resistor symmetry and performance.

FIGURE 7.

Proposed symmetrical S-R topology.

Show All

The model of the circuit in Fig. 7 can be easily derived by using the Bartlett’s theorem on the symmetrical structures after splitting $R_{p}$ into two series resistors each equal to $R_{p}$ /2. In fact, starting from the basic model reported in Fig. 5, we can obtain the model of the symmetrical S-R as shown in Fig. 8 in which the parasitic capacitance relative to $R_{p}$ is denoted as $C_{p}$ . The Y-parameters of symmetrical model have been computed referring to the equivalent circuit in Fig. 8 as shown below:

$$\begin{align*} Y{11}_{SYM}=&{Y_{11}}_{A}-\frac {Y_{\mathrm {21}A}*Y_{\mathrm {12}A}}{Y_{\mathrm {22}B}+Y_{\mathrm {22}A}}\tag{28}\\ Y{12}_{SYM}=&-\frac {Y_{\mathrm {21}B}*Y_{\mathrm {12}A}}{Y_{\mathrm {22}B}+Y_{\mathrm {22}A}}\tag{29}\\ Y{21}_{SYM}=&-\frac {Y_{\mathrm {21}A}*Y_{\mathrm {12}B}}{Y_{\mathrm {22}B}+Y_{\mathrm {22}A}}\tag{30}\\ Y{22}_{SYM}=&{Y_{11}}_{B}-\frac {Y_{\mathrm {21}B}*Y_{\mathrm {12}B}}{Y_{\mathrm {22}B}+Y_{\mathrm {22}A}}\tag{31}\end{align*}$$ View Source\begin{align*} Y{11}_{SYM}=&{Y_{11}}_{A}-\frac {Y_{\mathrm {21}A}*Y_{\mathrm {12}A}}{Y_{\mathrm {22}B}+Y_{\mathrm {22}A}}\tag{28}\\ Y{12}_{SYM}=&-\frac {Y_{\mathrm {21}B}*Y_{\mathrm {12}A}}{Y_{\mathrm {22}B}+Y_{\mathrm {22}A}}\tag{29}\\ Y{21}_{SYM}=&-\frac {Y_{\mathrm {21}A}*Y_{\mathrm {12}B}}{Y_{\mathrm {22}B}+Y_{\mathrm {22}A}}\tag{30}\\ Y{22}_{SYM}=&{Y_{11}}_{B}-\frac {Y_{\mathrm {21}B}*Y_{\mathrm {12}B}}{Y_{\mathrm {22}B}+Y_{\mathrm {22}A}}\tag{31}\end{align*}

FIGURE 8.

Model of the proposed symmetrical S-R.

Show All

It has be noted that, according to Fig. 8, the Yij parameters in (28)–(31) can be expressed as (14)–(17) by using ${R_{p}}/{2}$ in place of $R_{p}$ .

If the two TG switches are equally sized, then $Y_{ijA}=Y_{ijB}$ and the $Y_{SYM}$ matrix results symmetric with diagonal elements equal to each other. Starting from $Y_{SYM}$ , the complete $Y_{SYM,FULL}$ matrix including the parasitic capacitances of the TG switches can be easily computed and results symmetric too:

$$\begin{align*} Y_{SYM,FULL}=\left [{\begin{array}{lll} {Y11}_{SYM}+sC_{TG1} & {Y12}_{SYM} \\ {Y21}_{SYM} & {Y22}_{SYM}+sC_{TG1} \end{array} }\right].\tag{32}\end{align*}$$ View Source\begin{align*} Y_{SYM,FULL}=\left [{\begin{array}{lll} {Y11}_{SYM}+sC_{TG1} & {Y12}_{SYM} \\ {Y21}_{SYM} & {Y22}_{SYM}+sC_{TG1} \end{array} }\right].\tag{32}\end{align*}

To provide further validation of the S-R technique and of the proposed modeling approach, we designed a first-order low-pass filter (LPF) with tunable cutoff frequency and variable gain exploiting the tuning capability of Switched-Resistors.

The schematic of the designed first order active filter is shown in Fig. 9. The filter has been designed referring to the same 130nm CMOS process used in the previous sections: a MIM capacitor $C$ of 1pF and two polysilicon resistors $R_{1}=100k{\Omega }$ and $R_{2}\mathrm {=500}k{\Omega }$ have been taken from the technology library.

FIGURE 9.

First-order LPF-SR topology.

Show All

Minimum size n-MOS and p-MOS transistors have been used to implement the two TG switches in Fig. 9 (Wn/Ln = 150nm/130nm and Wp/Lp = 150nm/130nm), resulting in $R_{on}/R_{off}$ equal to $7.34k{\Omega }/166G{\Omega }$ respectively and $C_{TG1,2}$ about equal to 0.1fF.

The parasitic capacitances relative to $R_{1}$ and $R_{2}$ have been estimated as $C_{\mathrm {1}p1,2}\mathrm {=9.21}fF$ and $C_{\mathrm {2}p1,2}\mathrm {=45.1}fF$ respectively: $C_{TG1,2}$ are therefore negligible because they are three orders of magnitude smaller than $C_{\mathrm {1}p1,2}$ and $C_{\mathrm {2}p1,2}$ .

The clock frequency for the switched-resistors $R_{1}$ and $R_{2}$ has been set to $F_{ck}\mathrm {=10}kHz$ .

The schematic of the Operational Transconductance Amplifier (OTA) used in the filter is shown in Fig. 10. The first stage of the OTA is a telescopic cascode differential pair, whereas the second stage is a conventional common source stage with Miller compensation. The bias current $I_{ref}$ has been set to $2\mu A$ and the adopted supply voltage is 1V. Transistors dimensions and bias settings of the OTA are reported in Table 1. The designed OTA exhibits a dc-gain of about 75dB and a unity gain frequency in the order of a few MHz.

TABLE 1 Transistor Dimensions and Bias Settings for the OTA

FIGURE 10.

Single-ended OTA topology.

Show All

According to the conventional model of the S-R, the dc-gain $Gain_{dc}$ and the cutoff frequency $f_{cutoff}$ , of the active filter in Fig. 9 can be derived as:

View Source\begin{align*} \left |{Gain_{dc}\left ({\delta }\right)}\right |=&\frac {\frac {R_{2}+Ron}{\delta }}{\frac {R_{1}+Ron}{\delta }}=\frac {R_{2}+Ron}{R_{1}+Ron}\tag{33a}\\ f_{cutoff}\left ({\delta }\right)=&\frac {\delta }{2\pi \cdot \left ({R_{2}+Ron}\right)\cdot C}\tag{33b}\end{align*}

From (33a) it is evident that the conventional model predicts a constant dc-gain independent on the duty cycle $\delta$ , whereas, according to (33b), the cutoff frequency should be linearly dependent on $\delta$ . Both these predictions are not in agreement with simulations for low values of $\delta$ (see Fig. 14a), showing again the limitation of the conventional model applied to this case study.

FIGURE 11.

First-order LPF-SR model based on Y-matrix theory.

Show All

FIGURE 12.

Simulated frequency response with for ${\delta }$ = 10% and ${\delta }$ = 0.0001%.

Show All

FIGURE 13.

DC Gain of the active LPF: (a) comparison between the simulated gain and the proposed gain model; (b) relative error of the proposed gain model.

Show All

FIGURE 14.

Gain LPF- (a) Comparison of the simulated cutoff frequency with the detailed model and the conventional model; (b) relative error of the proposed cutoff frequency model.

Show All

Starting from the S-R model developed in the previous sections, we have developed the model of the full first order active filter reported in Fig. 9 referring to the equivalent circuit reported in Fig. 11. Since the focus of this paper is on the S-R model, we have used a very simple model for the OTA which is considered ideal, but with a finite open-loop gain ${K}$ .

With these assumptions, the frequency response of the active filter has been computed as:

View Source\begin{align*} \frac {V_{o}}{Vin}\left ({\delta,s}\right)=&\frac {-K Y_{21A}}{Y_{12B}K-Y_{11B}-Y_{22A}-sC\left ({1+K}\right)-s\left ({C_{2A}+C_{2B}}\right)}. \\ {}\tag{34}\end{align*}

$$\begin{align*} \left |{Gain_{dc}(\delta)}\right |=&\frac {KY_{21A}}{KY_{12B}-Y_{11B}-Y_{22A}}\tag{35a}\\ f_{cutoff}(\delta)=&\frac {1}{2\pi }\frac {\left ({Y_{12B}K-Y_{11B}-Y_{22A}}\right)}{\left ({C\left ({1+K}\right)+C_{2A}+C_{2B}}\right)}\tag{35b}\end{align*}$$ View Source\begin{align*} \left |{Gain_{dc}(\delta)}\right |=&\frac {KY_{21A}}{KY_{12B}-Y_{11B}-Y_{22A}}\tag{35a}\\ f_{cutoff}(\delta)=&\frac {1}{2\pi }\frac {\left ({Y_{12B}K-Y_{11B}-Y_{22A}}\right)}{\left ({C\left ({1+K}\right)+C_{2A}+C_{2B}}\right)}\tag{35b}\end{align*}

It is evident from Fig. 12 that the dc-gain drops from the ideal value of 13.5dB for $\delta$ = 10% to the much lower value of about −5dB for $\delta$ = 0.0001% due to the effect of parasitic capacitances which become dominant for $\delta$ = 0.0001%. In fact, the $\mathrm {500}k{\Omega }$ poly resistor $R_{2}$ exhibits a much higher parasitic capacitances than the $\mathrm {100}k{\Omega }$ poly resistor $R_{1}$ so that the ratio between the equivalent impedance of the S-R $R_{2}$ and of the S-R $R_{1}$ is lower than 1 when parasitic effects are dominant.

Fig. 13a reports the comparison between the dc gain of the active LPF obtained from PSS+PAC simulations and from the proposed gain model in (35a). The relative error of the model is shown in Fig. 13b.

By inspection of Fig. 13, it is evident that the conventional model in (33a) is not adequate to describe the gain of the LPF which exhibits more than 15dB of variation across the considered duty cycle range instead of being constant as predicted by (33a). On the other hand, the proposed gain model in (35a) is able to fit well the simulated gain curve with an average relative error of 3.17% and a maximum relative error of about 12% (despite the very simple model assumed for the OTA).

Fig. 14a reports the comparison between the cutoff frequency of the active LPF obtained from PSS+PAC simulations and from the proposed cutoff frequency model in (35b). The relative error of the model is shown in Fig. 14b.

By inspection of Fig. 14, it is evident that also in this case the conventional model is not able to predict the real dependence of $f_{cutoff}$ on $\delta$ , across the whole tuning range. The proposed model in (35b) is instead able to fit well the simulated cutoff frequency curve with an average error of 3.6% and a maximum error of 7%.

We have presented a detailed analysis of the Switched-Resistor technique, showing how the conventional model is not adequate to describe the equivalent resistance for very small values of the duty cycle. We have then proposed a novel, detailed model including the main parasitic effects, which is able to guarantee a very good accuracy even for duty cycle values as low as 0.0001%. The proposed modeling approach is useful to understand the real limitations of the S-R approach and to gain insight into the real behavior of switched-resistors. Furthermore, since the model is able to accurately predict the equivalent resistance as a function of the duty cycle, it allows to easily design the digital controller which sets the duty cycle in order to maximize the tuning range of cutoff frequency in active filters based on switched-resistors or to compensate PVT variations. To validate this last claim, an active, first order LPF has been implemented referring to a commercial 130nm CMOS technology showing a tuning range of the cutoff frequency about three decades (from 1.68Hz to 1.46kHz). Since the average error in the estimation of the cutoff frequency has resulted lower than 3.6% the relationship between the desired cutoff frequency and the duty cycle to set can be accurately predicted during the design phase.