Abstract:
Custom layout design style remains to be an effective way of improving and differentiating the performance of integrated circuits. In this paper, we revisit the classic p...Show MoreMetadata
Abstract:
Custom layout design style remains to be an effective way of improving and differentiating the performance of integrated circuits. In this paper, we revisit the classic problem of transistor chaining, a key step in transistor level layout generation and report a systematic method for permutating transistors in a circuit topology such that without altering its logic function, the chance of finding transistor chains with minimum number of diffusion breaks is increased. The results on nontrivial circuits show that our algorithm can consistently outperform the best reported results in the literature.
Published in: 2009 IEEE 8th International Conference on ASIC
Date of Conference: 20-23 October 2009
Date Added to IEEE Xplore: 11 December 2009
ISBN Information: