This paper describes the design and implementation of a linear optical receiver front-end for short range optical communication applications in 0.13-μm CMOS technology. While conventional optical receivers are typically implemented using limiting amplifiers (LA), emerging optical systems are expected to employ advanced modulation schemes, which require preserving the signal envelope. The proposed linear optical receiver architecture utilizes super-Gm transimpedance amplification with common-mode restoration and constant settling time automatic gain control (AGC) with background illumination cancellation to preserve the signal linearity while tolerating capacitance up to 15 pF for large area photo-detectors. Linearity aware design of transimpedance amplifiers (TIA), variable gain control (VGA), and post amplifiers (PA) are discussed before introducing an exponential generator based on the parasitic BJTs available in the used technology. Consuming 40 mW from a 1.2 V supply in the presence of ~15 pF input capacitance, the circuit achieves a binary modulation data rate of 5 Gbps with an input sensitivity of ~ 65 μA maintaining a bit-error rate (BER) <; 10^-12. S-parameter measurements show a constant -3 dB bandwidth of 2.5 GHz for a wide dynamic range of ~45 dB (30-75 dBΩ) with dB-linearity error better than ±1 dB. To demonstrate the optical functionality of the architecture, an external photodiode (PDCS70T-GS) is directly wirebonded to the chip. Optical measurements confirm a sensitivity of -9.5 dBm (BER <; 10^-12) at a highest data rate of 5 Gb/s (λ = 680 nm). The noise and linearity performance of the receiver is verified using input referred integrated noise and 1 dB-compression point measurements for different gain settings.