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A Survey on Neural Network Hardware Accelerators
IEEE Transactions on Artificial IntelligenceArtificial intelligence (AI) hardware accelerator is an emerging research for several applications and domains. The hardware accelerator's direction is to provide high computational speed with retaining low-cost and high learning performance.
Tamador Mohaidat, Kasem Khalil
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The design of startup accelerators
Research Policy, 2019Accelerator programs are an increasingly important part of entrepreneurial ecosystems. While accelerators have core defining features—fixed-term, cohort-based educational and mentorship programs for startups— there is also significant variation amongst ...
Susan L. Cohen +3 more
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Accelerated entropy estimates with accelerated dynamics
The Journal of Chemical Physics, 2007Accelerated dynamics is applied to entropy calculations on a set of toy and molecular systems and is found to enhance the rate of convergence.
David D L, Minh +2 more
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MAERI: Enabling Flexible Dataflow Mapping over DNN Accelerators via Reconfigurable Interconnects
International Conference on Architectural Support for Programming Languages and Operating Systems, 2018Deep neural networks (DNN) have demonstrated highly promising results across computer vision and speech recognition, and are becoming foundational for ubiquitous AI.
Hyoukjun Kwon, A. Samajdar, T. Krishna
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GAMMA: Automating the HW Mapping of DNN Models on Accelerators via Genetic Algorithm
2020 IEEE/ACM International Conference On Computer Aided Design (ICCAD), 2020DNN layers are multi-dimensional loops that can be ordered, tiled, and scheduled in myriad ways across space and time on DNN accelerators. Each of these choices is called a mapping.
Sheng-Chun Kao, T. Krishna
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Digital Versus Analog Artificial Intelligence Accelerators: Advances, trends, and emerging designs
IEEE Solid-State Circuits Magazine, 2022For state-of-the-art artificial intelligence (AI) accelerators, there have been large advances in both all-digital and analog/mixed-signal circuit-based designs.
J.-s. Seo +8 more
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Toward Functional Safety of Systolic Array-Based Deep Learning Hardware Accelerators
IEEE Transactions on Very Large Scale Integration (vlsi) Systems, 2021High accuracy and ever-increasing computing power have made deep neural networks (DNNs) the algorithm of choice for various machine learning, computer vision, and image processing applications across the computing spectrum.
Shamik Kundu +4 more
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PolyGraph: Exposing the Value of Flexibility for Graph Processing Accelerators
International Symposium on Computer Architecture, 2021Because of the importance of graph workloads and the limitations of CPUs/GPUs, many graph processing accelerators have been proposed. The basic approach of prior accelerators is to focus on a single graph algorithm variant (eg. bulk-synchronous + slicing)
Vidushi Dadu, Sihao Liu, Tony Nowatzki
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To accelerate or not to accelerate? That is the question
The Physics Teacher, 2010Thanks to Jim Hicks, Barrington High School, and Jaime Stasiorowski and Kristen Piggott, Deerfield High School, for their help with this month's column. If you have a YouTube video you use in class, please send the link and a brief description to: driendeau@dist113.org.
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A survey on modeling and improving reliability of DNN algorithms and accelerators
Journal of systems architecture, 2020As DNNs become increasingly common in mission-critical applications, ensuring their reliable operation has become crucial. Conventional resilience techniques fail to account for the unique characteristics of DNN algorithms/accelerators, and hence, they ...
Sparsh Mittal
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