Results 111 to 120 of about 503,882 (291)
Architectural Optimization of AES Transformations and Keyexpansion
Advanced Encryption Standard (AES), is a cryptographic algorithm used for data protection. Designing an efficient hardware architecture for AES with small hardware resource usage is a challenge. Many works are going on for the efficient implementation of
K. Rahimunnisa
core +1 more source
An all‐in‐one analog AI accelerator is presented, enabling on‐chip training, weight retention, and long‐term inference acceleration. It leverages a BEOL‐integrated CMO/HfOx ReRAM array with low‐voltage operation (<1.5 V), multi‐bit capability over 32 states, low programming noise (10 nS), and near‐ideal weight transfer.
Donato Francesco Falcone +11 more
wiley +1 more source
Detecting Hardware Trojans in Cryptography Devices Using Machine Learning
The current technological race to increase the volume of received, processed, and transmitted information plays a crucial role in the security of any country, as these areas are fundamental for the deployment of complex linguistic and experimental models,
A. Yu. Voronov, V. R. Stempitsky
doaj +1 more source
In MOCVD MoS2 memristors, a current compliance‐regulated Ag filament mechanism is revealed. The filament ruptures spontaneously during volatile switching, while subsequent growth proceeds vertically through the MoS2 layers and then laterally along the van der Waals gaps during nonvolatile switching.
Yuan Fa +19 more
wiley +1 more source
Instruction-Efficient and Parallelized AES using CUDA and PTX for Data Encryption
This research presents an instruction-efficient and parallelized implementation of the AES-256 encryption algorithm using NVIDIA CUDA with inline PTX to optimize instruction usage and execution performance on GPUs. Conventional AES implementation on CUDA
Raditya Hakim Daniswara +1 more
doaj +1 more source
L'algoritmo advanced encryption standard (AES) [PDF]
Descrizione dell'algoritmo crittografico AES, criteri adottati dal NIST per la scelta di AES e considerazioni sulla sua ...
Chieco, Davide
core
Integration of Low‐Voltage Nanoscale MoS2 Memristors on CMOS Microchips
This article presents the first monolithic integration of nanoscale MoS2‐based memristors into the back‐end‐of‐line of foundry‐fabricated CMOS microchips in a one‐transistor‐one‐resistor (1T1R) architecture. The MoS2‐based 1T1R cells exhibit forming‐free, nonvolatile resistive switching with ultra‐low operating voltages, low cycle‐to‐cycle variability ...
Jimin Lee +16 more
wiley +1 more source
Architectural Design of Referral Patient Data Security using Advanced Encryption Standard
Electronic medical record can manage various kinds of patient data in digital form. Patient data security is a priority that must be met by healthcare provider for referral process. One of the medical data exchange standards that is widely used is Health
Moh. Ali Romli, Muhammad Zakariyah
doaj +1 more source
Optoelectronic synaptic devices based on solution‐processed molecular telluride GST‐225 phase‐change inks are demonstrated for three‐factor learning. A global optical signal broadcast through a silicon waveguide induces non‐volatile conductance updates exclusively in locally electrically flagged memristors.
Kevin Portner +14 more
wiley +1 more source
Differential Fault Analysis of AES: Towards Reaching its Limits [PDF]
In this paper we present a theoretical analysis of the limits of the Differential Fault Analysis (DFA) of AES by developing an inter relationship between conventional cryptanalysis of AES and DFAs. We show that the existing attacks have not reached these
Michael Tunstall +5 more
core +1 more source

