Results 1 to 10 of about 6,329 (166)
A 12-Bit High-Speed Column-Parallel Two-Step Single-Slope Analog-to-Digital Converter (ADC) for CMOS Image Sensors [PDF]
Sensors, 2014 A 12-bit high-speed column-parallel two-step single-slope (SS) analog-to-digital converter (ADC) for CMOS image sensors is proposed. The proposed ADC employs a single ramp voltage and multiple reference voltages, and the conversion is divided into coarse
Tao Lyu +3 more
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A Stochastic Flash Analog-to-Digital Converter Linearized by Reference Swapping
IEEE Access, 2017 The linearity of a stochastic flash analog-to-digital converter (ADC) with two groups of comparators is improved by reference swapping. If the input offset of a comparator is larger than the linear input range of its comparator group, the reference ...
Min-Ki Jeon +3 more
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Expansion of dynamic range of sampling and storage device by weight integration of narrow-band oscillation [PDF]
Омский научный вестник, 2021 The most bottleneck of high-frequency digital radio receivers in terms of dynamic characteristics is the process of analog-to-digital conversion. Most often, to meet the requirements for the speed and dynamic range of the analog-to-digital conversion,
B. D. Zhenatov
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Recent Advances in High-Resolution Hybrid Discrete-Time Noise-Shaping ADCs
IEEE Open Journal of the Solid-State Circuits Society, 2021 High precision data acquisition requires very-high-resolution Analog-to-digital converters (ADC) for kHz speed or to keep a relatively high resolution for wider bandwidth (BW) around the MHz range.
Dongyang Jiang +4 more
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A 7.4-Bit ENOB 600 MS/s FPGA-Based Online Calibrated Slope ADC without External Components
Sensors, 2022 A slope analog-to-digital converter (ADC) amenable to be fully implemented on a digital field programmable gate array (FPGA) without requiring any external active or passive components is proposed in this paper.
Mengdi Zhang +6 more
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Analog to Digital Converters (ADC): A Literature Review [PDF]
E3S Web of Conferences, 2020 The signal processing is advancing day by day as its needs and in wireline/wireless communication technology from 2G to 4G cellular communication technology with CMOS scaling process. In this context the high-performance ADCs, analog to digital converters have snatched the attention in the field of digital signal processing.
Dalmia Hemlata, Sinha Sanjeet K.
openaire +2 more sources
Implementation of a digital trim scheme for SAR ADCs [PDF]
Advances in Radio Science, 2013 Successive approximation register (SAR) analog-to-digital Converters (ADC) are based on a capacitive digital-to-analog converter (CDAC) (McCreary and Gray, 1975).
J. Bialek +5 more
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Applied Sciences, 2022 In the high-resolution analog circuit, the performance of chips is an important part. The performance of the chips needs to be determined by testing. According to the test requirements, stimulus signal with better quality and performance is necessary ...
Li Wang +4 more
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Electronics Letters, 2022 The authors present a low‐power area‐efficient subarray beamforming receiver (RX) structure for a miniaturized 3‐D ultrasound imaging system. Given that the delay‐and‐sum (DAS) and digitization functions consume most of the area and power in the receiver,
Seungah Lee, Soohyun Yun, Joonsung Bae
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IEEE Access, 2021 A low-power 12-bit successive approximation register (SAR) analog-to-digital converter (ADC) with split-capacitor, nonbinary-weighted, and multiple-least-significant-bit (LSB)-redundant capacitor digital-to-analog converters (CDACs) is proposed.
Hsuan-Lun Kuo, Chih-Wen Lu, Poki Chen
doaj +1 more source