Results 31 to 40 of about 68,896 (280)
A 10-Bits 50-MS/s SAR ADC Based on Area-Efficient and Low-Energy Switching Scheme
IEEE Access, 2020 This paper presents a 10-bits successive approximation register analog-to-digital converter (SAR ADC) for low-power applications. The input signals are multiplied by two because the dual sampling technique is used during the sampling phase.
Chi-Chang Lu, Ding-Ke Huang
doaj +1 more source
Noise shaping Asynchronous SAR ADC based time to digital converter [PDF]
, 2018 Time-to-digital converters (TDCs) are key elements for the digitization of timing information in modern mixed-signal circuits such as digital PLLs, DLLs, ADCs, and on-chip jitter-monitoring circuits.
Katragadda, Sowmya
core +1 more source
Analog To Digital (Adc) And Digital To Analog (Dac) Converters [PDF]
1998 Annual Conference Proceedings, 2020 Comment: 12 ...
openaire +2 more sources
A Fully Differential CMOS Potentiostat [PDF]
, 2009 A CMOS potentiostat for chemical sensing in a noisy environment is presented. The potentiostat measures bidirectional electrochemical redox currents proportional to the concentration of a chemical down to pico-ampere range.
Genov, Roman, Nazari, Meisam Honarvar
core +1 more source
IEEE Access, 2020 A digital-controlled adaptive self-interference cancellation system with capabilities of high interference cancellation ratio and strong environmental applicability is presented.
Jinling Xing +4 more
doaj +1 more source
A Self-Calibration of Capacitor Mismatch Error for Pipeline ADCs
Applied Sciences, 2023 This study proposes self-calibration of capacitor mismatch errors for high-resolution pipeline analog-to-digital converters (ADCs). The proposed calibration circuit recursively amplifies the capacitor mismatch error by re-utilizing a multiplying digital ...
Dong-Hwan Seo +3 more
doaj +1 more source
14-bit 2.2-MS/s sigma-delta ADC's [PDF]
, 2000 This paper presents the design and test results of a fourth-order and sixth-order 14-bit 2.2-MS/s sigma-delta analog-to-digital converter (ADC). The analog modulator and digital decimator sections were implemented in a 0.35 μm CMOS double-poly triple ...
Geddie, C et al +3 more
core +2 more sources
A Stochastic Flash Analog-to-Digital Converter Linearized by Reference Swapping
IEEE Access, 2017 The linearity of a stochastic flash analog-to-digital converter (ADC) with two groups of comparators is improved by reference swapping. If the input offset of a comparator is larger than the linear input range of its comparator group, the reference ...
Min-Ki Jeon +3 more
semanticscholar +1 more source
Optics Express, 2016 We demonstrate a method to compensate multi-channel mismatches that intrinsically exist in a photonic analog-to-digital converter (ADC) system. This system, nominated time-wavelength interleaved photonic ADC (TWI-PADC), is time-interleaved via wavelength
Guang Yang +4 more
semanticscholar +1 more source
Comparator Design in Sensors for Environmental Monitoring [PDF]
, 2018 This paper presents circuit design considerations of comparator in analog-to-digital converters (ADC) applied for a portable, low-cost and high performance nano-sensor chip which can be applied to detect the airborne magnetite pollution nano particulate ...
Fan, Hua +4 more
core +1 more source