Results 71 to 80 of about 6,357 (228)

Experimental Demonstration of Temporally Aware Fault‐Tolerant Sensor Fusion Using Memristive Associative Learning

Advanced Electronic Materials, EarlyView.
In dynamic driving scenarios, the proposed approach ensures only temporally aligned sensor inputs to make driving decisions, preventing false activations. By enabling selective hardware‐level learning, it achieves fast, reliable responses under noisy conditions.
Kapil Bhardwaj, Ashfak Nehal, Dmitrii Semenov, Roman Sotner, Sayani Majumdar   +4 more
wiley   +1 more source

Toward Capacitive In‐Memory‐Computing: A Device to Systems Level Perspective on the Future of Artificial Intelligence Hardware

Advanced Intelligent Discovery, EarlyView.
Capacitive, charge‐domain compute‐in‐memory (CIM) stores weights as capacitance,eliminating DC sneak paths and IR‐drop, yielding near‐zero standbypower. In this perspective, we present a device to systems level performance analysis of most promising architectures and predict apathway for upscaling capacitive CIM for sustainable edge computing ...
Kapil Bhardwaj, Ella Paasio, Sayani Majumdar   +2 more
wiley   +1 more source

Time-Interleaved SAR ADC in 22 nm Fully Depleted SOI CMOS

Chips
This work presents the design and simulation of a time-interleaved successive approximation register (SAR) analog-to-digital converter (ADC) implemented in GlobalFoundries’ 22 nm Fully Depleted Silicon-on-Insulator (FD-SOI) CMOS process. Motivated by the
Trace Langdon, Jeff Dix
doaj   +1 more source

A Memristor‐Based In‐Memory Computing System‐on‐Chip with Efficient Depthwise Convolution

Advanced Intelligent Systems, EarlyView.
We present a memristor‐based in‐memory computing (IMC) architecture that enables efficient depthwise convolution (DWC) acceleration. Fabricated in a system‐on‐chip with crossbar arrays, the design improves memory utilization. Experimental validation demonstrates the first hardware acceleration of DWC in IMC, achieving a digital comparable inference ...
Wenhao Song, Fuxi Cai, Sangsu Park, Zhaoyan Li, Seonghun Lee, Mingyi Rao, Woohyung Choi, Seungin Shin, Yan Zhu, Sujin Chae, Myoungsub Kim, Mingche Wu, Hyejung Choi, Yuan Dao, Jaeyun Yi, Youngman Cho, Seon Yong Cha, Ning Ge, Qiangfei Xia, Soo Gil Kim, Miao Hu, J. Joshua Yang   +21 more
wiley   +1 more source

Pulse Compression Shape-Based ADC/DAC Chain Synchronization Measurement Algorithm with Sub-Sampling Resolution

Sensors
In this article, we address the problem of synchronizing multiple analog-to-digital converter (ADC) and digital-to-analog converter (DAC) chains in a multi-channel system, which is constrained by the sampling frequency and inconsistencies among the ...
Xiangyu Hao, Hongji Fang, Wei Luo, Bo Zhang   +3 more
doaj   +1 more source

Input Sparsity‐Aware Computing‐In‐Memory with Bidirectional Conversion‐Skippable Analog‐to‐Digital Converter

Advanced Intelligent Systems, EarlyView.
This article introduces an input sparsity‐aware computing‐in‐memory macro featuring novel bidirectional conversion‐skippable analog‐to‐digital converters. By dynamically adjusting resolution based on element‐level sparsity, the architecture skips redundant most significant bit and least significant bit conversions.
Choongseok Song, Yonguk Sim, Doo Seok Jeong   +2 more
wiley   +1 more source

MODUL ANALOG TO DIGITAL CONVERTER (ADC) 8 BIT DENGAN MENGGUNAKAN METODE SUCCESSIVE APROXIMATION REGISTER (SAR)

Protek: Jurnal Ilmiah Teknik Elektro, 2017
modul analog to digital converter (ADC) 8 bit dengan menggunakan metode successive aproximation register (SAR) merupakan sebuah alat yag dirancang dan dibuat untuk memenuhi salah satu persyaratan tugas akhir dan juga untuk melengkapi alat praktikum di ...
abdul rahmat laida
doaj   +1 more source

Neuromorphic Denoising with Fully Analog Memristive In‐Memory Computing

Advanced Intelligent Systems, EarlyView.
This article borrows the concepts of episodic memory in human brains to experimentally implement a memristor‐based neuromorphic denoising process. A homogeneous memristor processing unit is experimentally demonstrated for both temporal storage and neural network computation, imitating the synapses in the human brain.
Daijing Shi, Teng Zhang, Yuqi Li, Yaoyu Tao, Bonan Yan, Yuchao Yang   +5 more
wiley   +1 more source

Nonlinearity Analysis of Down-Sampled Paths in High-Speed ADC-Based SerDes Receivers

IEEE Access
Analog-to-Digital Converter (ADC) based Serializer- Deserializer (SerDes) receivers perform down-sampling in analog domain to address the speed limitation of the ADCs.
Archit Joshi
doaj   +1 more source

Design of a 6-bit Threshold Inverter Quantization (TIQ) Flash Analog to Digital Converter (ADC)

CoRR
An ADC is used to convert analog signals into binary signals. Compared with many other types of ADCs, flash converters are incredibly quick. A typical Flash ADC consists of 2n resistors, 2n-1 op-amp comparators, and an encoder which requires more area.
Noyon Kumar Sarkar, Moumita Roy, Md. Tariq Hasan   +2 more
openaire   +2 more sources