Results 71 to 80 of about 1,338 (209)

Let’s Get Physical: Rethinking the Static Partitioning Hypervisor Architecture for an MMU-Less Memory Model

IEEE Access
Many industries, in particular automotive, are undergoing substantial transformations in their underlying electrical and electronic architecture (E/E), pushing for a transition from traditional flat architectures to more decentralized and zonal systems ...
Afonso Santos, Jose Martins, Joao Sousa, Manuel Rodriguez, Sandro Pinto   +4 more
doaj   +1 more source

Look Before You Access: Efficient Heap Memory Safety for Embedded Systems on ARMv8-M

Design Automation Conference
Numerous embedded systems utilize firmware written in memory-unsafe C/C++. So, the firmware may exhibit spatial memory vulnerabilities, such as buffer overflows, which, if exploited by an attacker, can lead to various software attacks.
Jeonghwan Kang, Jaeyeol Park, Jiwon Seo, Donghyun Kwon   +3 more
semanticscholar   +1 more source

Fast white-box implementations of dedicated ciphers on the ARMv8 architecture

, 2020
Dedicated white-box ciphers concern the design of algorithms that withstand secret (key) extraction while executing in an insecure, fully explorable environment.
Rodrigues, F.C., Fujii, H., Sider, G., Dahab, R., López, J., Zoppi Serpa, A.C.   +5 more
core   +1 more source

Optimized Supersingular Isogeny Key Encapsulation on ARMv8 Processors [PDF]

, 2019
In this work, we present highly-optimized constant-time software libraries for Supersingular Isogeny Key Encapsulation (SIKE) protocol on ARMv8 processors. Our optimized hand-crafted assembly libraries provide the most efficient timing results on 64-bit
Reza Azarderakhsh, David Jao, Amir Jalali, Mehran Mozaffari Kermani, Matthew Campagna   +4 more
core   +1 more source

It’s TEEtime: Secure Interrupt Isolation for Normal-world Enclaves on Arm

Transactions on Cryptographic Hardware and Embedded Systems
Secure and direct peripheral access is an important building block for protecting sensitive applications on mobile and embedded devices: Otherwise, an untrusted OS or hypervisor can, for example, trivially intercept an app’s secrets when it renders them
Friederike Groschupp, Mark Kuhne, Moritz Schneider, Ivan Puddu, Shweta Shinde, Srdjan Capkun   +5 more
doaj   +1 more source

Accelerating Wait-Free Algorithms: Pragmatic Solutions on Cache-Coherent Multicore Architectures

IEEE Access, 2019
Parallelizing performance-critical applications are of critical importance for harnessing the power of multicore processors, which are now ubiquitous.
Junchang Wang, Qi Jin, Xiong Fu, Yun Li, Peichang Shi   +4 more
doaj   +1 more source

Measuring and Exploiting Guardbands of Server-Grade ARMv8 CPU Cores and DRAMs [PDF]

, 2018
In this paper, we present the results of our comprehensive measurement study of the timing and voltage guardbands in memories and cores of a commodity ARMv8 based micro-server.
Phong Vo, Lampropulos, Alejandro, Chatzidimitriou, Athanasios, Shidhartha, Mukhanov, Lev, Zacharias, Papadimitriou, George, Hadjilambrou, Kaliorakis, Manolis, Das, Gizopoulos, Dimitris, Karakonstantis, Georgios, Sazeides, Yiannakis, Tovletoglou, Konstantinos   +13 more
core   +3 more sources

User-space APIs for dynamic power management in many-core ARMv8 computing nodes [PDF]

, 2016
The push for energy-efficient and energy-proportional computing nodes, together with the increasing number of cores integrated in the same silicon die has lead to computing nodes with fine grained power management capabilities.
Tinti, Simone, Daniele Bortolotti, Bartolini, Andrea, Simone Tinti, Bortolotti, Daniele, Piero Altoe, Andrea Bartolini, Altoè, Piero   +7 more
core   +1 more source

Optimization of Direct Convolution Algorithms on ARM Processors for Deep Learning Inference

Mathematics
In deep learning, convolutional layers typically bear the majority of the computational workload and are often the primary contributors to performance bottlenecks.
Shang Li, Fei Yu, Shankou Zhang, Huige Yin, Hairong Lin   +4 more
doaj   +1 more source

Optimizing Sparse Matrix-Vector Multiplications on An ARMv8-based Many-Core Architecture [PDF]

, 2018
Sparse matrix–vector multiplications (SpMV) are common in scientific and HPC applications but are hard to be optimized. While the ARMv8-based processor IP is emerging as an alternative to the traditional x64 HPC processor design, there is little study on
Zheng Wang, Fang, Jianbin, Chuanfu Xu, Donglin Chen, Jianbin Fang, Xu, Chuanfu, Wang, Zheng, Chen, Shizhao, Chen, Donglin, Shizhao Chen   +9 more
core   +1 more source