Results 131 to 140 of about 115,723 (273)

Voltage-Polarity Dependent Programming Behaviors of Amorphous In–Ga–Zn–O Thin-Film Transistor Memory with an Atomic-Layer-Deposited ZnO Charge Trapping Layer

Nanoscale Research Letters, 2019
Amorphous In–Ga–Zn-O (a-IGZO) thin-film transistor (TFT) memories are attracting many interests for future system-on-panel applications; however, they usually exhibit a poor erasing efficiency.
Dan-Dan Liu, Wen-Jun Liu, Jun-Xiang Pei, Lin-Yan Xie, Jingyong Huo, Xiaohan Wu, Shi-Jin Ding   +6 more
doaj   +1 more source

“ALTIROC0, a 20 pico-second time resolution ASIC for the ATLAS High Granularity Timing Detector (HGTD)”

, 2018
ALTIROC0 is an 8-channel ASIC prototype designed to readout 1x1 or 2x2 mm2 50 µm thick Low Gain Avalanche Diodes (LGAD) of the ATLAS High Granularity Timing Detector (HGTD).
C. Taille, S. Callier, S. C. D. Lorenzo, N. Seguin-Moreau, P. Dinaucourt, G. Martin-Chassard, C. Agapopoulou, N. Makovec, L. Serin, S. Simion   +9 more
semanticscholar   +1 more source

An Economic Analysis of Difficulty Adjustment Algorithms in Proof‐of‐Work Blockchain Systems

International Economic Review, Volume 67, Issue 1, Page 259-285, February 2026.
ABSTRACT We study the stability of cryptocurrency systems through difficulty adjustment. Bitcoin's difficulty adjustment algorithm (DAA) exhibits instability when the reward elasticity of the hash rate is high, implying that a sharp price reduction could disrupt the current Bitcoin system.
Shunya Noda, Kyohei Okumura, Yoshinori Hashimoto   +2 more
wiley   +1 more source

A Commercially Available Digital Spectrometer ASIC

IEEE Journal of Selected Topics in Applied Earth Observations and Remote Sensing
This article presents a commercially available, low-power digital spectrometer application specific integrated circuit (ASIC). The ASIC computes 8192 frequency bins across the 4 GHz of resolvable bandwidth (488 kHz spectral resolution) and accumulates ...
Gytis Baranauskas, Paul Racette, Dalius Baranauskas, Denis Zelenin, Priscilla N. Mohammed   +4 more
doaj   +1 more source

The VeloPix ASIC

, 2017
VeloPix, a 130 nm CMOS technology chip with data driven and zero suppressed readout, will be used as a readout chip for the hybrid pixel system of the LHCb Vertex Locator (VELO) upgrade. The upgrade, scheduled for LHC Run-3, will enable the experiment to
T. Poikela, R. Ballabriga, J. Buytaert, X. Llopart, W. Wong, M. Campbell, K. Wyllie, M. Beuzekom, J. Schipper, S. Miryala, V. Gromov   +10 more
semanticscholar   +1 more source

Power Optimization for ASIC Design (Low power ASIC)

International Journal of Scientific Research in Science, Engineering and Technology, 2014
The modern era of embedded system design is geared toward the design of low-power systems. One way to reduce power in an application-specified integrated circuit (ASIC) implementation is to reduce feature size. Scaling of feature sizes in semiconductor technology has been responsible for increasingly higher computational capacity of silicon.
openaire   +1 more source

PSP: Parallel sub-pipelined architecture for high throughput AES on FPGA and ASIC

Open Computer Science, 2013
Rahimunnisa K., Karthigaikumar P., Christy N., Kumar S., Jayakumar J.   +4 more
doaj   +1 more source

Evaluation of an event-driven 3FI ASIC for spectroscopic X-ray detection with synchrotron radiation. [PDF]

J Synchrotron Radiat
Maj P, Deptuch GW, Gorni DS, Pinaroli G, Carini GA, Siddons DP, Tappero R, Mandal S, Pinelli D, Kersten T, St John N, Rumaiz AK, Kuczewski A.   +12 more
europepmc   +1 more source

Hardware Accelerators for Cardiovascular Signal Processing: A System-on-Chip Perspective. [PDF]

Micromachines (Basel)
Hariri R, Cirstea M, Oghaz MMD, Benkrid K, Faust O.   +4 more
europepmc   +1 more source

ASIC and FPGA based DPWM architectures for single-phase and single-output DC-DC converter: a review

Open Engineering, 2013
Chander Subhash, Agarwal Pramod, Gupta Indra   +2 more
doaj   +1 more source