Results 61 to 70 of about 115,723 (273)
IEEE Journal of Solid-State Circuits, 2018 This paper presents a front-end application-specified integrated circuit (ASIC) integrated with a 2-D PZT matrix transducer that enables in-probe digitization with acceptable power dissipation for the next-generation endoscopic and catheter-based 3-D ...
Chao Chen +10 more
semanticscholar +1 more source
A New Strategy to Design Reconfigurable Rivest–Shamir–Adleman (RSA) Accelerators
International Journal of Circuit Theory and Applications, EarlyView.A reconfigurable FPGA‐based RSA accelerator is proposed using compression‐based modular multipliers combined with pseudomoduli arithmetic. The approach maps modular exponentiation to low‐cost arithmetic domains and applies a correction stage, achieving significant improvements in delay, operating frequency, and delay–area efficiency compared with ...
Augusto C. B. Vassoler +4 more
wiley +1 more source
Implantable electronics of a closed-loop system for controlling prosthetic hands
Current Directions in Biomedical Engineering, 2017 This paper presents the design of implantable electronics as a part of a system for prosthetic hand control. Purpose of the implant is the sensing of electrical signals originating from biological tissue and the actuation of the same, therefore closing ...
Nikas Antonios +6 more
doaj +1 more source
Design and implementation of an energy-efficient Keccak algorithm ASIC
Dianzi Jishu Yingyong, 2019 The complete hardware circuit of Keccak algorithm which can support the four modes of SHA3 is designed and implemented. Based on the detailed analysis of the sponge functions and Keccak algorithm, the modular idea is used to divide the circuit structure ...
Tuo Zhao, Chen Tao, Li Wei, Nan Longmei
doaj +1 more source
A low-power, high-performance speech recognition accelerator [PDF]
, 2019 © 2019 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes,creating new ...
Arnau Montañés, José María +2 more
core +2 more sources
Design of an ASIC Digital Clock Using VLSI Technology
Applications of Modelling and Simulation, 2023 We present the design of an Application Specific Integrated Circuit (ASIC) digital clock based on the 0.12 µm deep submicron technology node. The widths of the PMOS and NMOS transistors are 0.72 µm and 0.24 µm, respectively.
Kim Ho Yeap +5 more
doaj
ASIC-Resistant Proof of Work Based on Power Analysis of Low-End Microcontrollers
Mathematics, 2020 Application-Specific Integrated Circuit (ASIC)-resistant Proof-of-Work (PoW) is widely adopted in modern cryptocurrency. The operation of ASIC-resistant PoW on ASIC is designed to be inefficient due to its special features.
Hyunjun Kim +3 more
doaj +1 more source
Nature Communications, 2021 Here, the authors demonstrate the application of machine learning to optimize the device fabrication process for wafer-scale 2D semiconductors, and eventually fabricate digital, analog, and optoelectrical circuits.
Xinyu Chen +33 more
doaj +1 more source
A 5.16Gbps decoder ASIC for Polar Code in 16nm FinFET [PDF]
International Symposium on Wireless Communication Systems, 2018 Polar codes has been selected as 5G standard. However, only a couple of ASIC featuring decoders are fabricated, and none of them support list size L > 4 and code length N > 1024. This paper presents an ASIC implementation of three decoders for polar code:
Xiaocheng Liu +6 more
semanticscholar +1 more source
Ketogenic diet for infantile epileptic spasms
Epilepsia Open, EarlyView.Abstract Approximately half of all cases of Infantile Epileptic Spasms Syndrome (IESS) do not respond to vigabatrin and hormonal therapies. There is no clear consensus as to the second‐line therapy for IESS. Ketogenic diet (KD) has emerged as an effective treatment for certain drug‐resistant epilepsies and in many cases of IESS.
Morris H. Scantlebury +3 more
wiley +1 more source