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Topics in balanced ternary designs
Bulletin of the Australian Mathematical Society, 1988zbMATH Open Web Interface contents unavailable due to conflicting licenses.
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Towards a balanced ternary FPGA
2009 International Conference on Field-Programmable Technology, 2009We propose and analyze an organization for a Field-Programmable Gate Array structure that operates using a balanced ternary logic system where the logic set {±1, 0} maps directly to equivalent voltage levels {±1.0V, 0.0V}. Circuits for basic components such as a ternary buffer, flip-flop and LUT are described based on the characteristics of a ...
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Balanced ternary designs with block size four
Journal of Statistical Planning and Inference, 1993A \(\text{BTD}(v,\rho_ 2,4,\lambda)\) is a balanced ternary design such that \(k=4\) and each element occurs two times in \(\rho_ 2\) blocks (and, of course, each pair of distinct elements occurs \(\lambda\) times in a block). A necessary existence condition for such a BTD is: if \(\lambda=2\) then \(v \geq 5 \rho_ 2+1\), if \(\lambda=3\) then \(v \geq
Billington, Elizabeth J. +2 more
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Some Constructions of Balanced Ternary Residual Treatment Effects Designs
Journal of Statistical Theory and Practice, 2010zbMATH Open Web Interface contents unavailable due to conflicting licenses.
Aggarwal, Manohar, Jha, Mithilesh Kumar
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Ternary Bitwise Balancing Analog-to-Digital Converter
2019 IEEE 2nd Ukraine Conference on Electrical and Computer Engineering (UKRCON), 2019In this paper are offered a method, algorithms and structural scheme of ternary ADC with bitwise balancing conversion type in order from the less significant bit to the most significant bit. This method allows to accelerate the conversion process, when the input signal is changing in the narrow bands defined by the specifics of the information sources ...
Petryshyn Mykhailo, Volodymyr Luzhetskyi
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Algorithms for Binary Coded Balanced and Ordinary Ternary Operations
IEEE Transactions on Computers, 1975A representation for binary coded ternary (BCT) numbers is proposed. This representation is then used for the introduction of algorithms for ternary addition and subtraction on binary hardware. In the algorithm introduced, distinction is made between basic algorithms, i.e., those which are independent of the type of the arithmetic, and those which are ...
Frieder, Gideon, Luk, Clement
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A note on partially balanced ternary designs
Periodica Mathematica Hungarica, 1988\textit{S. K. Mehta}, \textit{S. K. Agrawal} and \textit{A. K. Nigam} [Sankhyā, Ser. B 37, 211-219 (1975; Zbl 0382.05013)] have introduced partially balanced ternary designs and have given two methods of their construction. One from the incidence matrix of a PBIB design and another by multiplying the incidence matrix of a BIB design.
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Nonvolatile Balanced Ternary Memory Based on The Multiferroelectric Material GeSnTe2
The Journal of Physical Chemistry Letters, 2019Modern computer technology is based on the binary logic system. However, the slowdown of its development calls for transition to multivalued logic (MVL) systems. MVL can yield a denser logic implementation on the same chip area at low cost. More information can be transmitted with the same digits over fewer interconnections, thereby reducing power ...
Jisoo Nam +3 more
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More balanced ternary designs with block size four
Journal of Statistical Planning and Inference, 1987This paper gives necessary and sufficient conditions for the existence of balanced ternary designs with block size four and \(\Lambda =2\) in the cases \(\rho_ 2=3,4,5\) and 6; the cases \(\rho_ 2=1\) and 2 have appeared earlier.
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Balanced Ternary Logic Gates with Memristors
2022 29th IEEE International Conference on Electronics, Circuits and Systems (ICECS), 2022Diwan, Moin +3 more
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