Results 171 to 180 of about 7,247 (218)
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A sub-2.0 V BiCMOS logic circuit with a BiCMOS charge pump
IEEE Journal of Solid-State Circuits, 1996A BiCMOS logic circuit with very small input capacitance has been developed, which operates at low supply voltages. A High-beta BiCMOS (H/spl beta/-BiCMOS) gate circuit which fully utilizes the bipolar transistor features achieves 10 times the speed of a CMOS gate circuit with the same input capacitance and operating at 3.3 V supply voltage.
Hitoshi Okamura +6 more
exaly +2 more sources
Scaling of digital BiCMOS circuits
IEEE Journal of Solid-State Circuits, 1990A generalized first-order scaling theory for BiCMOS digital circuit structures is presented. The effect of horizontal, vertical, and voltage scaling on the speed performance of various BiCMOS circuits is presented. The generalized scaling theory is used for the MOSFET, and the constant collector current (CIC) scaling scheme is used for the bipolar ...
S H K Embabi, M I Elmasry
exaly +2 more sources
IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 1994
With the anticipated growth of BiCMOS technology for high-performance ASIC design, the issue of testing takes on great significance. This paper addresses the testing of BiCMOS logic circuits. Since many different implementations of BiCMOS gates have been proposed, four representative ones are studied.
Marc E. Levitt +2 more
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With the anticipated growth of BiCMOS technology for high-performance ASIC design, the issue of testing takes on great significance. This paper addresses the testing of BiCMOS logic circuits. Since many different implementations of BiCMOS gates have been proposed, four representative ones are studied.
Marc E. Levitt +2 more
openaire +1 more source
IEEE Journal of Solid-State Circuits, 1995
This paper proposes a BiCMOS wired-OR logic for high-speed multiple input logic gates. The logic utilizes the bipolar wired-OR to circumvent the use of a series connection of MOS transistors. The BiCMOS wired-OR logic was found to be the fastest compared with such conventional gates as CMOS NOR, BiCMOS multiemitter logic and CMOS wired-NOR logic, when ...
Yasunobu Nakase +4 more
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This paper proposes a BiCMOS wired-OR logic for high-speed multiple input logic gates. The logic utilizes the bipolar wired-OR to circumvent the use of a series connection of MOS transistors. The BiCMOS wired-OR logic was found to be the fastest compared with such conventional gates as CMOS NOR, BiCMOS multiemitter logic and CMOS wired-NOR logic, when ...
Yasunobu Nakase +4 more
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Proceedings., 1990 IEEE International Conference on Computer Design: VLSI in Computers and Processors, 2002
An advanced BiCMOS technology is used to build transceivers that provide incident edge switching on a Futurebus backplane with max prop delay time of 3 ns, and standby Icc of less than 4 mA. A Schottky diode between the driving transistor and the pad is reverse-biased so that pin capacitance is kept below 5 pf to minimize backplane loading.
T. Fletcher, E. Hahn, J. West
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An advanced BiCMOS technology is used to build transceivers that provide incident edge switching on a Futurebus backplane with max prop delay time of 3 ns, and standby Icc of less than 4 mA. A Schottky diode between the driving transistor and the pad is reverse-biased so that pin capacitance is kept below 5 pf to minimize backplane loading.
T. Fletcher, E. Hahn, J. West
openaire +1 more source
IBM Journal of Research and Development, 2002
Silicon technology development is at a crossroads, following an exponential rate of progress for more than thirty years. While CMOS (complementary metal-oxide-semiconductor) will remain the backbone of digital logic, silicon technology will evolve in directions driven by system needs that are not met by CMOS alone.
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Silicon technology development is at a crossroads, following an exponential rate of progress for more than thirty years. While CMOS (complementary metal-oxide-semiconductor) will remain the backbone of digital logic, silicon technology will evolve in directions driven by system needs that are not met by CMOS alone.
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BiCMOS: technology and circuit design
Microelectronics Journal, 1989Abstract In this paper, the state-of-the-art of combined bipolar/CMOS (BiCMOS) technologies and circuit techniques is described. Examples of advanced BiCMOS technologies for various applications will be given, together with theoretical considerations which allow a comparison of the bipolar and MOS transistors.
Zimmer, Günter +5 more
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European Transactions on Telecommunications, 1990
AbstractThis paper describes why and how BICMOS technology will be one of the top three technology stars of the next decade. After a presentation of the specific advantages and drawback5 of Bipolar and CMOS technologies, the exploitation of characteristics of both components. realized on the same chip, is discussed.
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AbstractThis paper describes why and how BICMOS technology will be one of the top three technology stars of the next decade. After a presentation of the specific advantages and drawback5 of Bipolar and CMOS technologies, the exploitation of characteristics of both components. realized on the same chip, is discussed.
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Multiemitter BiCMOS CML circuits
IEEE Journal of Solid-State Circuits, 1992New BiCMOS current-mode logic (CML) circuits employing multiemitter devices are proposed. They perform logic functions in addition to conversion from CMOS to CML (or ECL). Their transient behavior was analyzed, and their delay expressions were obtained and verified using HSPICE. These expressions were used to optimize their design.
Muhammad E. S. Elrabaa +1 more
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Test generation for BiCMOS circuits
1993 IEEE International Symposium on Circuits and Systems, 2002Stuck-ON faults in BiCMOS devices result in an enhanced I/sub DDQ/. Stuck-OPEN faults exhibit both sequential behavior and delay faults. Test generation is considered for stuck-ON and stuck-OPEN faults in BiCMOS circuits. A procedure for obtaining test vectors/sequences for testing of faults manifesting as enhanced I/sub DDQ/ delay faults and ...
Sankaran M. Menon +2 more
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