Results 181 to 190 of about 7,247 (218)
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Schottky merged BiCMOS structures
IEEE Journal of Solid-State Circuits, 1994A new merged BiCMOS structure is presented. It incorporates a Schottky diode between the base and the collector of the n-p-n bipolar transistor. The structure offers the same reduced area advantage of merged over conventional BiCMOS, and is shown to have granted latchup immunity to BiCMOS circuits. The device simulations using HSPICE verify the latchup
Samir S. Rofail, Mohamed I. Elmasry
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BiCMOS Silicon Photonics Platform
Optical Fiber Communication Conference, 2015Photonic BiCMOS is a new monolithic electronic-photonic integration technology, offering high-speed bipolar transistors together with broadband silicon photonics devices such as germanium detectors and depletion-type modulators. Integration aspects and first demonstrator examples shall be reviewed.
Lars Zimmermann +6 more
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BiCMOS domino: a novel high-speed dynamic BiCMOS logic
International Journal of Electronics, 1997A new BiCMOS dynamic logic family is presented. The logic gates provide a significant speed-up over existing logic families, such as, CMOS, BiCMOS and dynamic CMOS for the same feature size. The proposed logic family provides a high drive capability to drive large loads at higher speeds compared with the CMOS domino logic family.
SANKARAN M. MENON +2 more
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Proceedings of IEEE VLSI Test Symposium, 1995
Opens in BiCMOS structures are analyzed here. It is shown that some opens cannot be detected by stuck-fault or other functional tests, since some transistors in BiCMOS gates do not affect the logical function of the gate. A switch-level model for CMOS circuits is extended to include bipolar devices.
Siyad C. Ma, Edward J. McCluskey
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Opens in BiCMOS structures are analyzed here. It is shown that some opens cannot be detected by stuck-fault or other functional tests, since some transistors in BiCMOS gates do not affect the logical function of the gate. A switch-level model for CMOS circuits is extended to include bipolar devices.
Siyad C. Ma, Edward J. McCluskey
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Proceedings., Second Annual IEEE ASIC Seminar and Exhibit, 2003
The objective of Hi-BiCMOS is to combine speed performance approaching that of ECL and integration density approaching that of CMOS. A high-performance 1.3- mu m BiCMOS technology and its applications to ASICs (application-specific integrated circuits) are described. This Hi-BiCMOS gate array contains 3072 gates and 90 input/output buffers.
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The objective of Hi-BiCMOS is to combine speed performance approaching that of ECL and integration density approaching that of CMOS. A high-performance 1.3- mu m BiCMOS technology and its applications to ASICs (application-specific integrated circuits) are described. This Hi-BiCMOS gate array contains 3072 gates and 90 input/output buffers.
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BiCMOS current source reference network for ULSI BiCMOS with ECL circuitry
IEEE International Solid-State Circuits Conference, 2003A BiCMOS current source reference network which eliminates the impact of DC power supply voltage drops on the operation of ECL (emitter coupled logic) circuits is described. This is essential for implementing ECL design techniques in ULSI BiCMOS circuits.
H.V. Tran, P.K. Fung, D.B. Scott
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1990
BiCMOS technology combines Bipolar and CMOS transistors in a single integrated circuit. By retaining the benefits of Bipolar and CMOS, BiCMOS is able to achieve VLSI circuits with speed-power-density performance previously unattainable with either technology individually.
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BiCMOS technology combines Bipolar and CMOS transistors in a single integrated circuit. By retaining the benefits of Bipolar and CMOS, BiCMOS is able to achieve VLSI circuits with speed-power-density performance previously unattainable with either technology individually.
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Design and scaling of BiCMOS circuits
Proceedings 1992 IEEE International Conference on Computer Design: VLSI in Computers & Processors, 2003A design procedure for sizing all devices in multi-input BiCMOS gates is presented. The notion of an equivalent inverter is introduced, and the optimal ratio of P to N MOSFETs in this inverter is observed to be a constant dependent only on the technology.
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[1992] Proceedings of the 35th Midwest Symposium on Circuits and Systems, 2003
Design issues associated with developing an analog BiCMOS process technology are reviewed. This information is then highlighted with an example of BiCMOS process stressing modularity and component diversity. Future technology issues for next-generation processes are discussed. >
L. Hutter, J. Smith, J. Goon
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Design issues associated with developing an analog BiCMOS process technology are reviewed. This information is then highlighted with an example of BiCMOS process stressing modularity and component diversity. Future technology issues for next-generation processes are discussed. >
L. Hutter, J. Smith, J. Goon
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BiCMOS—Circuits and Technology
IETE Technical Review, 1990BiCMOS which combines CMOS and bipolar circuits for high performance together with high density and low power has been recognised to be the emerging silicon technology. This paper brings out the compatibility of present day VLSI CMOS and bipolar technologies and discusses the orientations necessary for optimization of devices and circuits involved ...
S Kal, V G Pawar, N B Chakrabarti
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