Results 161 to 170 of about 18,840,038 (173)
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A 14nm logic technology featuring 2nd-generation FinFET, air-gapped interconnects, self-aligned double patterning and a 0.0588 µm2 SRAM cell size
2014 IEEE International Electron Devices Meeting, 2014 S. Natarajan, M. Agostinelli, S. Akbar, M. Bost, A. Bowonder, V. Chikarmane, S. Chouksey, A. Dasgupta, K. Fischer, Q. Fu, T. Ghani, M. Giles, S. Govindaraju, R. Grover, W. Han, D. Hanken, E. Haralson, M. Haran, M. Heckscher, R. Heussner, P. Jain, R. James, R. Jhaveri, I. Jin, H. Kam, E. Karl, C. Kenyon, Mark Y. Liu, Y. Luo, R. Mehandru, S. Morarka, L. Neiberg, P. Packan, A. Paliwal, C. Parker, P. Patel, R. Patel, C. Pelto, L. Pipes, P. Plekhanov, M. Prince, S. Rajamani, J. Sandford, B. Sell, S. Sivakumar, P. J. Smith, B. Song, K. Tone, T. Troeger, J. Wiedemer, M. Yang, Kevin Zhang +51 moresemanticscholar +1 more sourceAn enhanced 16nm CMOS technology featuring 2nd generation FinFET transistors and advanced Cu/low-k interconnect for low power and high performance applications
2014 IEEE International Electron Devices Meeting, 2014 S. Wu, C. Y. Lin, M. Chiang, J. Liaw, J. Cheng, S. Yang, S. Chang, M. Liang, T. Miyashita, C. Tsai, C. H. Chang, V. Chang, Y. Wu, J. H. Chen, H. Chen, S. Chang, K. Pan, R. F. Tsui, C. Yao, K. Ting, T. Yamamoto, H. Huang, T. L. Lee, C. Lee, W. Chang, H. M. Lee, C. C. Chen, T. Chang, R. Chen, Y. Chiu, M. Tsai, S. Jang, K. Chen, Y. Ku +33 moresemanticscholar +1 more sourceA 7nm FinFET technology featuring EUV patterning and dual strained high mobility channels
International Electron Devices Meeting, 2016 R. Xie, P. Montanini, K. Akarvardar, N. Tripathi, B. Haran, S. Johnson, T. Hook, B. Hamieh, D. Corliss, J. Wang, Xin He Miao, J. Sporre, J. Fronheiser, N. Loubet, M. Sung, S. Sieg, S. Mochizuki, C. Prindle, S. Seo, A. Greene, J. Shearer, A. Labonté, S. Fan, L. Liebmann, R. Chao, A. Arceo, K. Chung, K. Cheon, P. Adusumilli, H. Amanapu, Z. Bi, J. Cha, H. Chen, R. Conti, R. Galatage, O. Gluschenkov, V. Kamineni, K. Kim, C. Lee, F. Lie, Z. Liu, S. Mehta, E. Miller, H. Niimi, C. Niu, C. Park, D. Park, M. Raymond, B. Sahu, M. Sankarapandian, S. Siddiqui, R. Southwick, L. Sun, C. Surisetty, S. Tsai, S. Whang, P. Xu, Y. Xu, C. Yeh, P. Zeitzoff, J. Zhang, J. Li, J. Demarest, J. Arnold, D. Canaperi, D. Dunn, N. Felix, D. Gupta, H. Jagannathan, S. Kanakasabapathy, W. Kleemeier, C. Labelle, M. Mottura, P. Oldiges, S. Skordas, T. Standaert, T. Yamashita, M. Colburn, M. Na, V. Paruchuri, S. Lian, R. Divakaruni, T. Gow, S. Lee, A. Knorr, H. Bu, M. Khare +86 moresemanticscholar +1 more sourceFour-layer 3D vertical RRAM integrated with FinFET as a versatile computing unit for brain-inspired cognitive information processing
2016 IEEE Symposium on VLSI Technology, 2016 Haitong Li, Kai-Shin Li, Chang-Hsien Lin, Juo-Luen Hsu, W. Chiu, Min-Cheng Chen, Tsung-Ta Wu, Joon Sohn, S. Eryilmaz, J. Shieh, W. Yeh, H.-S. Philip Wong +11 moresemanticscholar +1 more sourceA novel junctionless FinFET structure with sub-5nm shell doping profile by molecular monolayer doping and microwave annealing
2014 IEEE International Electron Devices Meeting, 2014 Y. Lee, Ta-Chun Cho, K. Kao, P. Sung, F. Hsueh, P. Huang, C. Wu, Shu‐Han Hsu, W. Huang, H. Chen, Y. Li, M. Current, B. Hengstebeck, J. Marino, T. Buyuklimanli, J. Shieh, T. Chao, W. Wu, W. Yeh +18 moresemanticscholar +1 more sourceA low operating power FinFET transistor module featuring scaled gate stack and strain engineering for 32/28nm SoC technology
International Electron Devices Meeting, 2010 C. Yeh, Chih-Sheng Chang, Hong-Nien Lin, W. Tseng, L. Lai, T. Perng, Tsung-Lin Lee, Chang-Yun Chang, L. Yao, Chia-Cheng Chen, T. Kuan, Jeff J. Xu, C. Ho, Tzu-Chiang Chen, Shyue-Shyh Lin, H. Tao, M. Cao, Chih-Hao Chang, T. Ko, N. Chen, Shih-Cheng Chen, Chia-Pin Lin, Hsien-Chin Lin, Ching-Yu Chan, H.T. Lin, Shu-ting Yang, J.C. Sheu, C. Fu, Shih-Ting Hung, F. Yuan, M. Shieh, Chia-Feng Hu, C. Wann +32 moresemanticscholar +1 more source
