Results 1 to 10 of about 5,722 (215)
Comparison of bulk FinFET and SOI FinFET [PDF]
MATEC Web of Conferences, 2018 In this study, we compare the differences and advantages between Bulk FinFET and SOI FinFET. The results are simulated by using the ISE TCAD software.
Chen Ying-Yu, Lin Yu-Hsien
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Comparative Study of Novel u-Shaped SOI FinFET Against Multiple-Fin Bulk/SOI FinFET
IEEE Access, 2023 Superior scalability and better gate-to-channel capacitive coupling can be achieved with adopting gate-all-around (GAA) device architecture. However, compared against FinFET device structure, the GAA device is not very cost-effective.
Myoungsu Son +3 more
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Nanomaterials, 2023 This research presents the optimization and proposal of P- and N-type 3-stacked Si0.8Ge0.2/Si strained super-lattice FinFETs (SL FinFET) using Low-Pressure Chemical Vapor Deposition (LPCVD) epitaxy.
Guang-Li Luo, Fu-Ju Hou, Yung-Chun Wu
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Comparative Leakage Analysis of GeOI FinFET and Ge Bulk FinFET [PDF]
IEEE Transactions on Electron Devices, 2013 We present a comparative leakage analysis of germanium-on-insulator (GeOI) FinFET and germanium on bulk substrate FinFET (Ge bulk FinFET) at device and circuit levels. Band-to-band tunneling (BTBT) leakage-induced bipolar effect is found to result in an amplified BTBT leakage for GeOI FinFET.
Vita Pi-Ho Hu, Ming-Long Fan, Pin Su
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Micromachines, 2022 In this work, we propose a vertical gate-all-around device architecture (GAA-FinFET) with the aim of simultaneously improving device performance as well as addressing the short channel effect (SCE).
Changwoo Noh +3 more
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Analysis of the Dispersion of Electrical Parameters and Characteristics of FinFET Devices
Journal of Telecommunications and Information Technology, 2023 Extensive numerical simulations of FinFET structures have been carried out using commercial TCAD tools. A series of plasma etching steps has been simulated for different process conditions in order to evaluate the influence of plasma pressure ...
Arkadiusz Malinowski +6 more
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Overview of FinFET device structure development
Dianzi Jishu Yingyong, 2021 With the rapid development of integrated circuit technology, the size of devices continues to shrink. When the channel of the field effect transistor is shortened to 22 nm, the traditional planar field effect transistor no longer meets the development ...
Xiong Qian, Ma Kui, Yang Fashun
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BSIM-CMG compact model for IC CAD: from FinFET to Gate-All-Around FET Technology
Journal of Microelectronic Manufacturing, 2020 We discuss the BSIM-CMG compact model for SPICE simulations of any common multi-gate (CMG) device. This is an industry standard model which has been used extensively for FinFETs IC design and simulation, and has now been extended to accurately model gate-
Avirup Dasgupta, Chenming Hu
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Design Technology Co-Optimization Strategy for Ge Fraction in SiGe Channel of SGOI FinFET
Nanomaterials, 2023 FinFET devices and Silicon-On-Insulator (SOI) devices are two mainstream technical routes after the planar MOSFET reached the limit for scaling. The SOI FinFET devices combine the benefits of FinFET and SOI devices, which can be further boosted by SiGe ...
Shixin Li, Zhenhua Wu
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Micromachines, 2022 In this work, we present a radio frequency (RF) assessment of the nanoscale gallium nitride-silicon-on-insulator fin field-effect transistor (GaN-SOI-FinFET). All the performances of the device were compared with GaN-FinFET and conventional FinFET (Conv.
Ajay Kumar +3 more
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