Results 41 to 50 of about 5,722 (215)
FinFET SRAM hardening through design and technology parameters considering process variations [PDF]
, 2013 Radiation-induced soft errors have become one of the most important reliability concerns in the nanometer regime. In this paper, we analyze two alternatives to improve FinFET-based SRAM cell hardening.
Víctor Hugo Champac Vilela +1 more
core
Physical Modeling and Design of a Nonvolatile Optically Gated High‐Power Diamond Transistor
physica status solidi (a), Volume 223, Issue 11, 10 June 2026.We introduce a diamond optically gated field effect transistor (DOGFET) which combines high‐speed high‐power operation with exotic single transistor memory. The transistor uses deep level donor type nitrogen traps in type 1b diamond that are optically excited to enable electrostatic gating of the device.
Soumak Nandi +9 more
wiley +1 more source
, 2010 Scaling bulk CMOS SRAM technology for on-chip caches beyond the 22nm node is questionable, on account of high leakage power consumption, performance degradation, and instability due to process variations.
Niraj K. Jha, Ajay N. Bhoj
core +1 more source
MFMIS Negative Capacitance FinFET Design for Improving Drive Current
, 2020 The effect of remnant polarization (Pr), coercive electric-field (Ec), and parasitic capacitance of baseline device on the drive current (ION) of a metal-ferroelectric-metal-insulator-semiconductor (MFMIS) negative capacitance FinFET (NC FinFET) was ...
Jinhong Min, Changhwan Shin
core +1 more source
Comprehensive analysis of In0.53Ga0.47As SOI-FinFET for enhanced RF/wireless performance
Frontiers in ElectronicsThis paper comprehensively analyses the RF (Radio Frequency) and wireless performance characteristics of high-k In0.53Ga0.47As silicon-on-insulator FinFET (InGaAs-SOI-FinFET).
Priyanka Agrwal, Ajay Kumar
doaj +1 more source
A Cross-Layer Framework for Designing and Optimizing Deeply-Scaled FinFET-Based Cache Memories
Journal of Low Power Electronics and Applications, 2015 This paper presents a cross-layer framework in order to design and optimize energy-efficient cache memories made of deeply-scaled FinFET devices. The proposed design framework spans device, circuit and architecture levels and considers both super- and ...
Alireza Shafaei +3 more
doaj +1 more source
Review of Nanosheet Transistors Technology
Tikrit Journal of Engineering Sciences, 2021 Nano-sheet transistor can be defined as a stacked horizontally gate surrounding the channel on all direction. This new structure is earning extremely attention from research to cope the restriction of current Fin Field Effect Transistor (FinFET ...
Firas .. Agha +2 more
doaj +1 more source
Advanced Materials Interfaces, Volume 13, Issue 11, 9 June 2026.Plasma‐sequence‐engineered ALD (PSE‐ALD), based on sequential NH3 and N2 plasma pulses, enables ultrathin, dense SiNx films. ToF‐MS analysis confirms ligand removal via HCl evolution, while increased film density indicates network densification. The resulting SiNx coating provides robust protection of graphite under H2 plasma exposure.
Hye‐Young Kim +7 more
wiley +1 more source
Partial Isolation Type Saddle-FinFET(Pi-FinFET) for Sub-30 nm DRAM Cell Transistors
, 2018 In this paper, we proposed a novel saddle type FinFET (S-FinFET) to effectively solve problems occurring under the capacitor node of a dynamic random-access memory (DRAM) cell and showed how its structure was superior to conventional S-FinFETs in terms ...
Young Kwon Kim +7 more
core +1 more source
Elektronika ir ElektrotechnikaThis paper presents high-frequency universal filter applications based on a voltage differential buffered amplifier (VDBA) using 32 nm fin field effect transistor (FinFET) technology.
Sevda Altan Yagci +2 more
doaj +1 more source