Results 51 to 60 of about 7,054 (167)
Advanced Intelligent Systems, EarlyView.A training‐free two‐stage BO–RL framework extracts compact model parameters for a‐IGZO TFTs, reaching BO‐level fitting quality at a constant per‐simulation optimization cost. Bayesian optimization performs exploration and provides an optimized starting point.
Seunghyun Son +4 more
wiley +1 more source
Elektronika ir ElektrotechnikaThis paper presents high-frequency universal filter applications based on a voltage differential buffered amplifier (VDBA) using 32 nm fin field effect transistor (FinFET) technology.
Sevda Altan Yagci +2 more
doaj +1 more source
Revisiting Dopant Deactivation In Silicon Nanostructures
Advanced Physics Research, EarlyView.Dopant activation is essential for the operation of semiconductor devices. On the nanoscale, however, quantum confinement and dielectric mismatch impede dopant activation. Here, we study the ionization of phosphorous in ultrathin silicon films embedded in different dielectric environments.
J. Knoch +4 more
wiley +1 more source
FinFET SRAM hardening through design and technology parameters considering process variations [PDF]
, 2013 Radiation-induced soft errors have become one of the most important reliability concerns in the nanometer regime. In this paper, we analyze two alternatives to improve FinFET-based SRAM cell hardening.
Víctor Hugo Champac Vilela +1 more
core
Comprehensive analysis of In0.53Ga0.47As SOI-FinFET for enhanced RF/wireless performance
Frontiers in ElectronicsThis paper comprehensively analyses the RF (Radio Frequency) and wireless performance characteristics of high-k In0.53Ga0.47As silicon-on-insulator FinFET (InGaAs-SOI-FinFET).
Priyanka Agrwal, Ajay Kumar
doaj +1 more source
A Cross-Layer Framework for Designing and Optimizing Deeply-Scaled FinFET-Based Cache Memories
Journal of Low Power Electronics and Applications, 2015 This paper presents a cross-layer framework in order to design and optimize energy-efficient cache memories made of deeply-scaled FinFET devices. The proposed design framework spans device, circuit and architecture levels and considers both super- and ...
Alireza Shafaei +3 more
doaj +1 more source
Small Methods, EarlyView.Electrolyte‐gated nanoscale silicon field‐effect transistor sensors provide exceptional charge sensitivity and direct electrical readout. However, their sensing accuracy is fundamentally limited by low‐frequency noise and baseline drift. This review examines the origins of noise and drift in these sensors, summarizes the key mitigation strategies, and ...
Yingtao Yu +5 more
wiley +1 more source
MFMIS Negative Capacitance FinFET Design for Improving Drive Current
, 2020 The effect of remnant polarization (Pr), coercive electric-field (Ec), and parasitic capacitance of baseline device on the drive current (ION) of a metal-ferroelectric-metal-insulator-semiconductor (MFMIS) negative capacitance FinFET (NC FinFET) was ...
Jinhong Min, Changhwan Shin
core +1 more source
An Innovative Approach to Multi‐Valued Logic
IEEJ Transactions on Electrical and Electronic Engineering, EarlyView.The current generation of computer systems operates on the principles of binary logic, which encompasses both logical and arithmetic operations. However, silicon technology has reached its peak performance, prompting researchers to explore alternative methods for enhancing computational efficiency. One such method is the adoption of Multi‐Valued Logic (
Ali Mokhtari, Peyman Kabiri
wiley +1 more source
Partial Isolation Type Saddle-FinFET(Pi-FinFET) for Sub-30 nm DRAM Cell Transistors
, 2018 In this paper, we proposed a novel saddle type FinFET (S-FinFET) to effectively solve problems occurring under the capacitor node of a dynamic random-access memory (DRAM) cell and showed how its structure was superior to conventional S-FinFETs in terms ...
Young Kwon Kim +7 more
core +1 more source