Silicon-on-Insulator (SOI) Lateral Power-Reduced Surface Field FinFET with High-Power Figure of Merit of 239.3 MW/cm2 [PDF]
MicromachinesIn this study, we propose a lateral power-reduced surface field FinFET (LPR-FinFET) to achieve high breakdown voltage and low on-resistance. We investigate the electric field distribution within the reduced surface field (RESURF) structure under reverse ...
Chang Woo Song +4 more
doaj +2 more sources
Multi-Channel Step FinFET With Spacer Engineering
IEEE AccessMulti-channel FinFET ( $\text{M}_{\textbf {ch}}$ -FinFET) is an emerging device having promising use due to its excellent driving capability. In this paper, we have investigated the significance of multiple channels of FinFET configuration.
Rinku Rani Das, Alex James
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Role of mechanical stress on the electrothermal and OFF state current in scaled FinFET devices [PDF]
Scientific ReportsThe electrothermal characteristics and leakage current of a tall FinFET device were investigated using the hydrodynamic transport model coupled with a quantum-corrected diffusive transport mechanism-based TCAD simulation.
Shubham, Rajan Kumar Pandey
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Low Power and Energy‐Efficient Design of MTJ/FinFET Circuits
Engineering ReportsAs technological nodes are scaled down to the nanoscale, power consumption emerges as a critical challenge in complementary metal‐oxide‐semiconductor (CMOS) technology.
Pillem Ramesh, Atul S. M. Tripathi
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Carrier Mapping in Sub‐2nm Node Nanosheet Transistors with Scanning Spreading Resistance Microscopy [PDF]
Small Methods, Volume 10, Issue 5, 9 March 2026.Within this work, advancements in scanning spreading resistance microscopy (SSRM) allow charge carrier mapping within 5.5 nm‐thick nanosheet channels. Devices subjected to rapid thermal annealing at 950°C show ∼ 5 nm enhanced phosphorus diffusion, with profiles in close agreement with semi‐atomistic process simulations.
Andrea Pondini +7 more
wiley +2 more sources
High performance and low leakage heterojunction 10 nm PZT NC-FinFET for low power application [PDF]
Scientific ReportsIncreasing transistor integration density and increased power are the significant challenges for designers at lower transistor technology nodes. However, scaling down the transistor leads to the uneven change in threshold voltage with scaled supply ...
Suman Lata Tripathi +3 more
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Simulation Study on the Charge Collection Mechanism of FinFET Devices in Single-Event Upset [PDF]
MicromachinesPlanar devices and FinFET devices exhibit significant differences in single-event upset (SEU) response and charge collection. However, the charge collection process during SEU in FinFET devices has not been thoroughly investigated. This article addresses
Hongwei Zhang +6 more
doaj +2 more sources
A Stepped-Spacer FinFET Design for Enhanced Device Performance in FPGA Applications [PDF]
MicromachinesAs transistor dimensions continue to scale below 10 nm, traditional MOSFET architectures face increasing limitations from short-channel effects, gate leakage, and variability.
Meysam Zareiee +2 more
doaj +2 more sources
Study of finfet transistor: critical and literature review in finfet transistor in the active filter
3C TIC: Cuadernos de desarrollo aplicados a las TIC, 2023 For several decades, the development of metal-oxide-semiconductor field-effect transistors have made available to us better circuit time and efficiency per function with each successive generation of CMOS technology. However, basic product and manufacturing technology limitations will make continuing transistor scaling difficult in the sub-32 nm zone ...
Mahmood, Zaidoon Khalaf +2 more
openaire +3 more sources
, 2010 [spa] El presente articulo pretende dar a conocer los dispositivos FinFET, que ventajas presenta su estructura frente a los dispositivos MOS clásicos, cual es el estado del arte actual y finalmente, cual es el impacto de este tipo de transistor en el mercado.
Mas Boned, Francisco de Borja +1 more
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