Results 101 to 110 of about 489,919 (293)
Approaches to Stand-alone Verification of Multicore Microprocessor Caches
Труды Института системного программирования РАН, 2018 The paper presents an overview of approaches used in verifying correctness of multicore microprocessors caches. Common properties of memory subsystem devices and those specific to caches are described. We describe the method to support memory consistency
M. . Petrochenkov +2 more
doaj +1 more source
Image‐Based Spatio‐Temporal Interpolation for Split Rendering
Computer Graphics Forum, EarlyView.Abstract Low‐powered devices – such as small form factor head‐mounted displays (HMDs) – struggle to deliver a smooth and high‐quality viewing experience, due to their limited power and rendering capabilities. Cloud rendering attempts to solve the quality issue, but leads to prohibitive latency and bandwidth requirements, hindering use with HMDs over ...
M. Steiner +4 more
wiley +1 more source
Test environment for verification of multi-processor memory subsystem unit
Труды Института системного программирования РАН, 2019 State of the art microprocessor systems usually include complex hierarchy of a cache memory. Coherence protocols are used to maintain memory consistency.
Dmitry Alexeevitch Lebedev +1 more
doaj +1 more source
Children &Society, EarlyView.ABSTRACT Social inequality shapes society and influences how children grow up. This study explores how wealthy young individuals in Germany perceive social inequality, focusing on their awareness of both wealth and poverty. In‐depth interviews revealed that their understanding of poverty is relatively simplified, shaped largely by a lack of direct ...
Johanna Wilmes, Sonja A. Gossenauer
wiley +1 more source
Research on Linux network packet buffer recycling toward multi-core processor
Tongxin xuebao, 2009 A lock-free algorithm for Linux packet buffer recycling on multi-core processor was proposed.Through making a model of Linux network packet forwarding, the principle of Linux packet buffer recycling was analyzed, and the main reason that the mechanism ...
YAO Qi +3 more
doaj +2 more sources
Decoupling Cache Coherence From XML in Model Checking [PDF]
, 2018 Many electrical engineers would agree that, had it not been for link-level acknowledgements, the eval- uation of congestion control might never have occurred.
Krishnakumar, S. (Suraj) +1 more
core
The Economic History Review, EarlyView.Abstract During the global economic crisis of 1929–33, deposits in the Dutch commercial banking sector sharply declined as funds shifted to the government‐guaranteed Post Office Savings Bank and other savings institutions. Unlike earlier studies for neighbouring countries, we demonstrate that this shift was driven less by a flight to safety and more by
Ruben Peeters +1 more
wiley +1 more source
Centering, Anaphora Resolution, and Discourse Structure [PDF]
, 1997 Centering was formulated as a model of the relationship between attentional state, the form of referring expressions, and the coherence of an utterance within a discourse segment (Grosz, Joshi and Weinstein, 1986; Grosz, Joshi and Weinstein, 1995).
Walker, Marilyn A.
core +2 more sources
Perspectives on Time and Personality: Philip G. Zimbardo (1934–2024) in Memoriam
Journal of Personality, EarlyView.ABSTRACT The present paper aims to honor the memory of one of the most notable figures in psychological science over the past five decades, Philip G. Zimbardo, who sadly passed away in late 2024. To this end, we provide a multi‐perspective view on psychological time—a topic that deeply engaged Phil Zimbardo during the later stages of his prolific ...
Maciej Stolarski +7 more
wiley +1 more source
Design Principles for Scaling Multi-core OLTP Under High Contention
, 2016 Although significant recent progress has been made in improving the multi-core scalability of high throughput transactional database systems, modern systems still fail to achieve scalable throughput for workloads involving frequent access to highly ...
Abadi, Daniel J. +2 more
core +1 more source