Results 1 to 10 of about 263,258 (207)
CASY: A CPU Cache Allocation System for FaaS Platform
2022 22nd IEEE International Symposium on Cluster, Cloud and Internet Computing (CCGrid), 2022 Function as a Service (FaaS) has become a key service in the cloud. It enables customers to conceive their appli-cation as a collection of minimal serverless functions interacting with each other.
Armel Jeatsa +2 more
exaly +3 more sources
Finite Automata Implementations Considering CPU Cache
Acta Polytechnica, 2007 The finite automata are mathematical models for finite state systems. More general finite automaton is the nondeterministic finite automaton (NFA) that cannot be directly used.
J. Holub
doaj +4 more sources
Super-Scalar RAM-CPU Cache Compression [PDF]
22nd International Conference on Data Engineering (ICDE'06), 2006 High-performance data-intensive query processing tasks like OLAP, data mining or scientific data analysis can be severely I/O bound, even when high-end RAID storage systems are used. Compression can alleviate this bottleneck only if encoding and decoding speeds significantly exceed RAID I/O bandwidth.
Marcin Zukowski +3 more
openaire +2 more sources
In-cache query co-processing on coupled CPU-GPU architectures [PDF]
Proceedings of the VLDB Endowment, 2014 Recently, there have been some emerging processor designs that the CPU and the GPU (Graphics Processing Unit) are integrated in a single chip and share Last Level Cache (LLC). However, the main memory bandwidth of such coupled CPU-GPU architectures can be much lower than that of a discrete GPU.
Jiong He +2 more
openaire +3 more sources
Method of Timing Attack for Linux Against KASLR [PDF]
Jisuanji gongcheng, 2021 For Linux systems with Kernel Address Space Layout Randomization(KASLR) protection, this paper proposes a Cache instant attack method based on CPU prefetch instruction.
CONG Mou, ZHANG Ping, WANG NING
doaj +1 more source
Enabling Atomic Durability for Persistent Memory with Transiently Persistent CPU Cache [PDF]
arXiv.org, 2022 Persistent memory (pmem) products bring the persistence domain up to the memory level. Intel recently introduced the eADR feature that guarantees to flush data buffered in CPU cache to pmem on a power outage, thereby making the CPU cache a transient ...
Chongnan Ye +3 more
semanticscholar +1 more source
Secur. Commun. Networks, 2021 Privacy protection is an essential part of information security. The use of shared resources demands more privacy and security protection, especially in cloud computing environments.
Chao Su, Qingkai Zeng
semanticscholar +1 more source
Hierarchical cache configuration based on hybrid SOT- and STT-MRAM
AIP Advances, 2023 With the rapid growth of big data information and the continuous iteration progress of CPU architecture, the implementation of a new memory-based cache architecture is urgent and challenging. In the paper, a CPU cache architecture system based on MRAM is
Shaopu Han, Qiguang Wang, Yanfeng Jiang
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Evaluating associativity in CPU caches [PDF]
IEEE Transactions on Computers, 1989 The authors present new and efficient algorithms for simulating alternative direct-mapped and set-associative caches and use them to quantify the effect of limited associativity on the cache miss ratio. They introduce an algorithm, forest simulation, for simulating alternative direct-mapped caches and generalize one, which they call all-associativity ...
Mark D. Hill, Alan Jay Smith
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Two novel cache management mechanisms on CPU-GPU heterogeneous processors
Research Briefs on Information & Communication Technology Evolution, 2021 Heterogeneous multicore processors that take full advantage of CPUs and GPUs within the same chip raise an emerging challenge for sharing a series of on-chip resources, particularly Last-Level Cache (LLC) resources.
Huijing Yang, Tingwen Yu
doaj +1 more source