Results 11 to 20 of about 263,258 (207)
Reuse Cache for Heterogeneous CPU-GPU Systems
CoRR, 2021 It is generally observed that the fraction of live lines in shared last-level caches (SLLC) is very small for chip multiprocessors (CMPs). This can be tackled using promotion-based replacement policies like re-reference interval prediction (RRIP) instead of LRU, dead-block predictors, or reuse-based cache allocation schemes. In GPU systems, similar LLC
Tejas Shah +3 more
openaire +2 more sources
JackHammer: Efficient Rowhammer on Heterogeneous FPGA-CPU Platforms
Transactions on Cryptographic Hardware and Embedded Systems, 2020 After years of development, FPGAs are finally making an appearance on multi-tenant cloud servers. Heterogeneous FPGA-CPU microarchitectures require reassessment of common assumptions about isolation and security boundaries, as they introduce new attack ...
Zane Weissman +5 more
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High-Performance and Flexible Design Scheme with ECC Protection in the Cache
Micromachines, 2022 To improve the reliability of static random access memory (SRAM), error-correcting codes (ECC) are typically used to protect SRAM in the cache. While improving the reliability, we also need additional circuits to support ECC, including encoding and ...
Yulun Zhou +3 more
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IET Communications, EarlyView., 2022 Abstract The goal of this work is to investigate how the self‐awareness characteristic of autonomic computing, paired with existing performance optimization rules, may be used in applications to minimise multi‐core processor performance concerns. The suggested self‐awareness technique can assist applications in self‐execution while also assisting other
Surendra Kumar Shukla +8 more
wiley +1 more source
Precision planter monitoring system based on mobile communication network
IET Networks, EarlyView., 2022 Abstract Sowing is an important link in agricultural production and the basis for ensuring high yields and bumper harvests. Agriculture requires precision plows with good performance and stable work. However, the seeding process is in a completely closed state, and the operator relies mainly on experience to judge the operating state and performance of
Bing Li, Jiyun Li
wiley +1 more source
A Conversation History-Based Q&A Cache Mechanism for Multi-Layered Chatbot Services
Applied Sciences, 2021 Chatbot technologies have made our lives easier. To create a chatbot with high intelligence, a significant amount of knowledge processing is required. However, this can slow down the reaction time; hence, a mechanism to enable a quick response is needed.
Ozoda Makhkamova, Doohyun Kim
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Large-capacity and high-speed instruction cache based on divide-by-2 memory banks
Journal of Electronic Science and Technology, 2021 An increase in the cache capacity is usually accompanied by a decrease in access speed. To balance the capacity and performance of caches, this paper proposes an instruction cache (ICache) architecture based on divide-by-2 memory banks (D2MB-ICache). The
Qing-Qing Li +4 more
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Real-Time Detection for Cache Side Channel Attack using Performance Counter Monitor
Applied Sciences, 2020 Cache side channel attacks extract secret information by monitoring the cache behavior of a victim. Normally, this attack targets an L3 cache, which is shared between a spy and a victim.
Jonghyeon Cho +5 more
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To use or not to use: CPUs' cache optimization techniques on GPGPUs [PDF]
2016 IEEE International Conference on Information and Automation for Sustainability (ICIAfS), 2016 6 pages, 15 ...
Vajira Thambawita +2 more
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On the Incomparability of Cache Algorithms in Terms of Timing Leakage [PDF]
Logical Methods in Computer Science, 2019 Modern computer architectures rely on caches to reduce the latency gap between the CPU and main memory. While indispensable for performance, caches pose a serious threat to security because they leak information about memory access patterns of programs ...
Pablo Cañones, Boris Köpf, Jan Reineke
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