Results 11 to 20 of about 489,919 (293)
HeteroGen: Automatic Synthesis of Heterogeneous Cache Coherence Protocols
International Symposium on High-Performance Computer Architecture, 2022 We solve the two challenges architects face when designing heterogeneous processors with cache coherent shared memory. First, we develop an automated tool, called HeteroGen, for composing clusters of cores, each with its own coherence protocol.
Nicolai Oswald +5 more
semanticscholar +1 more source
MSI-A: An Energy Efficient Approximated Cache Coherence Protocol
IEEE Access, 2023 Energy consumption has become an essential factor in designing modern computer system architecture. Because of physical limits, the termination of Moore’s law and Dennard’s scaling has forced the computer design community to investigate new
Anant Saraswat +3 more
doaj +1 more source
WiDir: A Wireless-Enabled Directory Cache Coherence Protocol
International Symposium on High-Performance Computer Architecture, 2021 As the core count in shared-memory manycores keeps increasing, it is becoming increasingly harder to design cache-coherence protocols that deliver high performance without an inordinate increase in complexity and cost.
Antonio Franques +5 more
semanticscholar +1 more source
Proposal New Cache Coherence Protocol to Optimize CPU Time through Simulation Caches [PDF]
Engineering and Technology Journal, 2016 The cache coherence is the most important issue that rapidly affected the performance of a multicore processor as a result of increasing the number of cores on chip multiprocessors and the shared memory program that will be run on these processors ...
Luma Fayeq Jalil +2 more
doaj +1 more source
A novel approach to parameterized verification of cache coherence protocols
ICCD, 2016 Yongjian Li +4 more
openalex +3 more sources
Extending Magny-Cours Cache Coherence [PDF]
IEEE Transactions on Computers, 2012 One cost-effective way to meet the increasing demand for larger high-performance shared-memory servers is to build clusters with off-the-shelf processors connected with low-latency point-to-point interconnections like HyperTransport. Unfortunately, HyperTransport addressing limitations prevent building systems with more than eight nodes.
Ros Bardisa, Alberto +7 more
openaire +3 more sources
Design and implementation of geographic information system with mobile terminal and 5G network
IET Networks, EarlyView., 2022 Abstract Remote insurance mainly completes quotation, insurance application and payment through the PC terminal and mobile terminal, and the premium directly enters the insurance account. This article takes remote insurance as an example. First, it analyses the requirements of the remote insurance and insurance system, and then collects data from the ...
Huijun Xiao, Tangsen Huang, Ensong Jiang
wiley +1 more source
Reducing Cache Coherence Traffic with a NUMA-Aware Runtime Approach
IEEE Transactions on Parallel and Distributed Systems, 2017 Paul Caheny +5 more
openalex +3 more sources
Cache Coherence for GPU Architectures [PDF]
IEEE Micro, 2013 While scalable coherence has been extensively studied in the context of general purpose chip multiprocessors (CMPs), GPU architectures present a new set of challenges. Introducing conventional directory protocols adds unnecessary coherence traffic overhead to existing GPU applications.
I. Singh +4 more
openaire +1 more source
Fractal Coherence: Scalably Verifiable Cache Coherence [PDF]
2010 43rd Annual IEEE/ACM International Symposium on Microarchitecture, 2010 We propose an architectural design methodology for designing formally verifiable cache coherence protocols, called Fractal Coherence. Properly designed to be fractal in behavior, the proposed family of cache coherence protocols can be formally verified correct for systems with an arbitrary number of cores, using existing, automated formal tools.
Meng Zhang +2 more
openaire +1 more source