Cache coherence - Open Access .click

IEEE Transactions on Computers, 2015
In this paper we introduce ICCI, a new cache organization that leverages shared cache resources and flat coherence protocols to provide inexpensive hardware cache coherence for large core counts (e.g., 512), achieving execution times close to a non-scalable sparse directory while noticeably reducing the energy consumption of the memory system.
Antonio Garcia-Guirado +2 more
openaire +2 more sources

Designing Predictable Cache Coherence Protocols for Multi-Core Real-Time Systems

IEEE transactions on computers, 2021
This article addresses the challenge of allowing simultaneous and predictable accesses to shared data on multi-core systems. We propose a collection of predictable cache coherence protocols, which mandate the use of certain design invariants to ensure ...
A. Kaushik, Mohamed Hassan, Hiren D. Patel +2 more
semanticscholar +1 more source

A Systematic Approach to Achieving Tight Worst-Case Latency and High-Performance Under Predictable Cache Coherence

IEEE Real Time Technology and Applications Symposium, 2021
Predictable hardware cache coherence is an attractive data communication mechanism between safety-critical tasks deployed on real-time multi-core platforms due to its predictability and high-performance benefits.
A. Kaushik, Hiren D. Patel
semanticscholar +1 more source

Zero Directory Eviction Victim: Unbounded Coherence Directory and Core Cache Isolation

International Symposium on High-Performance Computer Architecture, 2021
A directory structure is traditionally employed for tracking coherence information of the privately cached blocks in a cache-coherent chip-multiprocessor (CMP).
Mainak Chaudhuri
semanticscholar +1 more source

cache
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mesi protocol

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