Results 221 to 230 of about 489,919 (293)

HMG: Extending Cache Coherence Protocols Across Modern Hierarchical Multi-GPU Systems

International Symposium on High-Performance Computer Architecture, 2020
Prior work on GPU cache coherence has shown that simple hardware-or software-based protocols can be more than sufficient. However, in recent years, features such as multi-chip modules have added deeper hierarchy and non-uniformity into GPU memory systems.
X. Ren, Daniel Lustig, Evgeny Bolotin, A. Jaleel, Oreste Villa, D. Nellans   +5 more
semanticscholar   +1 more source

Web cache coherence

Computer Networks and ISDN Systems, 1996
All Web caches must try to keep cached pages up to date with the master copies of those pages, to avoid returning stale pages to users. In traditional distributed systems terminology, the problem of keeping cached pages up to date is called coherence.
Adam Dingle, Tomáš Pártl
openaire   +1 more source

Software caching on cache-coherent multiprocessors

[1992] Proceedings of the Fourth IEEE Symposium on Parallel and Distributed Processing, 2003
The authors explore the utility of software caching on a machine with coherent caches. In particular, they show that by caching at the application level one can avoid the problem of false sharing on cache-coherent machines. They compare the performance of software caching with that of other techniques for alleviating false sharing and show that ...
R. Bianchini, T.J. LeBlanc
openaire   +1 more source

No cache-coherence

Proceedings of the 46th Annual Design Automation Conference, 2009
Consistent with the trend towards the use of many cores in SOC and 3D Chip techniques, this paper proposes a "single-cycle ring" interconnection (SC_Ring) with ultra-low latency and minimal complexity. The proposed SC_Ring allows multiple single-cycle transactions in parallel.
Shu-Hsuan Chou, Chien-Chih Chen, Chi-Neng Wen, Yi-Chao Chan, Tien-Fu Chen, Chao-Ching Wang, Jinn-Shyan Wang   +6 more
openaire   +1 more source

Adjustable block size coherent caches

ACM SIGARCH Computer Architecture News, 1992
Several studies have shown that the performance of coherent caches depends on the relationship between the granularity of sharing and locality exhibited by the program and the cache block size. Large cache blocks exploit processor and spatial locality, but may cause unnecessary cache invalidations due to false sharing. Small cache blocks can reduce the
Czarek Dubnicki, Thomas J. LeBlanc
openaire   +1 more source

Exploiting cache affinity in software cache coherence

Proceedings of the 8th international conference on Supercomputing - ICS '94, 1994
Cache affinity is important to the performance of scalable shared memory multiprocessors. For multiprocessors without hardware cache coherence support, software cache coherence is the only alternative. Most existing software cache schemes ignore cache affinity across parallel loops.
Hui Li, Kenneth C. Sevcik
openaire   +1 more source

NoC-Based Support of Heterogeneous Cache-Coherence Models for Accelerators

ACM/IEEE International Symposium on Networks-on-Chips, 2018
On-chip shared memory is the primary paradigm for multi-core SoC designs and poses the most critical challenges to their scalability. Choosing the appropriate coherence model for accelerators not only can improve the overall system performance, but can ...
Davide Giri, Paolo Mantovani, L. Carloni
semanticscholar   +1 more source

Predictable Cache Coherence for Multi-core Real-Time Systems

IEEE Real Time Technology and Applications Symposium, 2017
This work addresses the challenge of allowing simultaneous and predictable accesses to shared data on multicore systems. We propose a predictable cache coherence protocol, which mandates the use of certain invariants to ensure predictability.
Mohamed Hassan, A. Kaushik, Hiren D. Patel   +2 more
semanticscholar   +1 more source

In-Network Cache Coherence

IEEE Computer Architecture Letters, 2006
We propose implementing cache coherence protocols within the network, demonstrating how an in-network implementation of the MSI directory-based protocol allows for in-transit optimizations of read and write delay. Our results show 15% and 24% savings on average in memory access latency for SPLASH-2 parallel benchmarks running on a 4times4 and a ...
Noel Eisley, Li-shiuan Peh, Li Shang
openaire   +1 more source

Design and Implementation of Cache Coherence Protocol for High-Speed Multiprocessor System

IEEE International Conference on Power Electronics, Intelligent Control and Energy Systems, 2018
To maintain data consistency between the cache memories in centralized and distributed shared-memory multiprocessor system, particular protocols are used known as cache coherence protocols.
Damanpreet Kaur, V. Sulochana
semanticscholar   +1 more source