Results 231 to 240 of about 489,919 (293)

Variable granularity cache coherence

ACM SIGOPS Operating Systems Review, 1994
Weak connectivity is characterized by slow or intermittent networks. Distributed file systems using weak connections must function in spite of limited bandwidth and frequent connectivity changes. Callback-based cache coherence schemes were designed to minimize client-server communication, but with an underlying assumption that the network ...
L. Mummert, M. Satyanarayanan
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Hardware Cache Coherence Protocol

International Journal of Computers and Applications, 2004
This article describes a new hardware cache coherence protocol based on sequential consistency. The protocol uses the directory scheme and invalidation strategy.
M. Daoui, M. Lalam, B. Djamah, A. Bilami
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Checking Cache-Coherence Protocols with TLA+

Formal Methods in System Design, 2003
zbMATH Open Web Interface contents unavailable due to conflicting licenses.
Joshi, Rajeev, Lamport, Leslie, Matthews, John, Tasiran, Serdar, Tuttle, Mark, Yu, Yuan   +5 more
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Effects of Cache Coherency in Multiprocessors

IEEE Transactions on Computers, 1982
In many commercial multiprocessor systems, each processor accesses the memory through a private cache. One problem that could limit the extensibility of the system and its performance is the enforcement of cache coherence. A mechanism must exist which prevents the existence of several different copies of the same data block in different private caches.
Dubois, Michel, Briggs, Faye A.
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Verifying cache coherence protocols

IEEE Spectrum, 1996
The shared-memory multiprocessor architecture is becoming prevalent in high-end servers designed to handle many users or large parallel computations. In such a machine, several parallel processors share a common store. To avoid communications bottlenecks, each processor has its own local cache memory that stores recently accessed data from the shared ...
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Efficient Timestamp-Based Cache Coherence Protocol for Many-Core Architectures

International Conference on Supercomputing, 2016
As we enter the era of many-core, providing the shared memory abstraction through cache coherence has become progressively difficult. The de-facto standard directory-based cache coherence has been extensively studied; but it does not scale well with ...
Yuan Yao, Guanhua Wang, Zhiguo Ge, T. Mitra, Wenzhi Chen, Naxin Zhang   +5 more
semanticscholar   +1 more source

Power-Efficient Cache Coherence

2004
Snoopy coherence implementations employ various forms of speculation to reduce cache miss latency and improve performance. We study the effects of reduced speculation on both performance and power consumption in a scalable snooping design. We find that significant potential exists for reducing energy consumption by using serial snooping for load misses.
Craig Saldanha, Mikko H. Lipasti
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Parallelism-Aware High-Performance Cache Coherence with Tight Latency Bounds

Euromicro Conference on Real-Time Systems, 2022
Reza Mirosanlou, Mohamed Hassan, R. Pellizzoni   +2 more
semanticscholar   +1 more source

SCI (Scalable Coherent Interface) Cache Coherence

1990
SCI — Scalable Coherent Interface — is the name of a local or extended computer “backplane” interface, being defined by an active IEEE Standard (P1596). The interconnect is scalable, meaning that up to 64K processor, memory, or I/O nodes can effectively interface to a shared SCI interconnect.
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Improved-MOESI Cache Coherence Protocol

Arabian Journal for Science and Engineering, 2013
The cache coherence protocol plays an important role in the performance of distributed and centralized shared-memory multiprocessors. A variety of bus-based cache coherence protocols exist and differ mainly in the way they respond to the transactions, and the bus transition state.
Hesham Altwaijry, Diyab S. Alzahrani
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