Results 21 to 30 of about 489,919 (293)
A Primer on Memory Consistency and Cache Coherence, Second Edition
A Primer on Memory Consistency and Cache Coherence, 2020 Many modern computer systems, including homogeneous and heterogeneous architectures, support shared memory in hardware.
Vijay Nagarajan +3 more
semanticscholar +1 more source
On the Implementation of a Formal Method for Verification of Scalable Cache Coherent Systems
Труды Института системного программирования РАН, 2018 This article analyzes existing methods of verification of cache coherence protocols of scalable systems. Based on the research literature, the paper describes a method of formal parameterized verification of safety properties of cache coherence protocols.
Vladimir Burenkov
doaj +1 more source
MESI Cache Coherence Simulator for Teaching Purposes
CLEI Electronic Journal, 2009 Nowadays, the computational systems (multi and uniprocessors) need to avoid the cache coherence problem. There are some techniques to solve this problem. The MESI cache coherence protocol is one of them.
Juan Gómez-Luna +2 more
doaj +1 more source
On How to Identify Cache Coherence: Case of the NXP QorIQ T4240
Euromicro Conference on Real-Time Systems, 2020 Architectures used in safety critical systems have to pass certain certification standards, which require sufficient proof that they will behave as expected.
Nathanaël Sensfelder +2 more
semanticscholar +1 more source
Distributed data cache designs for clustered VLIW processors [PDF]
, 2005 Wire delays are a major concern for current and forthcoming processors. One approach to deal with this problem is to divide the processor into semi-independent units referred to as clusters.
Gibert Codina, Enric +2 more
core +2 more sources
ARCc: A case for an architecturally redundant cache-coherence architecture for large multicores [PDF]
, 2011 This paper proposes an architecturally redundant cache-coherence architecture (ARCc) that combines the directory and shared-NUCA based coherence protocols to improve performance, energy and dependability.
Agarwal, Anant +5 more
core +2 more sources
HieraGen: Automated Generation of Concurrent, Hierarchical Cache Coherence Protocols
International Symposium on Computer Architecture, 2020 We present HieraGen, a new tool for automatically generating hierarchical cache coherence protocols. HieraGen’s inputs are the simple, atomic, stable state protocols for each level of the hierarchy.
Nicolai Oswald +2 more
semanticscholar +1 more source
Study the Influential Factors in the Hit Rate of Cache Memory for a Multiprocessors System
Tikrit Journal of Engineering Sciences, 2016 This paper presents an analytical and deductive study at software and hardware level for a symmetric multiprocessors system. Basic influential factors in the performance as cache memory size, processors number, and coherence protocols of cache memories ...
Ammar A. Zaqzuq
doaj +3 more sources
RC3: Consistency Directed Cache Coherence for x86-64 with RC Extensions
International Conference on Parallel Architectures and Compilation Techniques, 2015 Marco Elver, Vijay Nagarajan
openalex +3 more sources
ACM Transactions on Reconfigurable Technology and Systems, 2012 Asymmetric coherency is a new optimization method for coherency policies to support nonuniform workloads in multicore processors. Asymmetric coherency assists in load balancing a workload and this is applicable to SoC multicores where the applications are not evenly spread among the processors and customization of the coherency is possible.
Shield, John +2 more
openaire +1 more source