Results 31 to 40 of about 489,919 (293)
Cache Coherence Scheme for HCS-Based CMP and Its System Reliability Analysis
IEEE Access, 2017 In previous work, a new network switch architecture, hybrid circuit-switched (HCS) network, has been proposed and evaluated. In doing so, it has been studied for use in a multi-processor system, with a focus on power and throughput.
Sizhao Li, Donghui Guo
doaj +1 more source
Developing a Multicore Platform Utilizing Open RISC-V Cores
IEEE Access, 2021 RISC-V has been experiencing explosive growth since its first appearance in 2011. Dozens of free and open cores developed based on this instruction set architecture have been released, and RISC-V based devices optimized for specific applications such as ...
Hyeonguk Jang +6 more
doaj +1 more source
CoNDA: Efficient Cache Coherence Support for Near-Data Accelerators
International Symposium on Computer Architecture, 2019 Specialized on-chip accelerators are widely used to improve the energy efficiency of computing systems. Recent advances in memory technology have enabled near-data accelerators (NDAs), which reside off-chip close to main memory and can yield further ...
Amirali Boroumand +10 more
semanticscholar +1 more source
Local Search and the Evolution of World Models
Topics in Cognitive Science, EarlyView., 2023 Abstract An open question regarding how people develop their models of the world is how new candidates are generated for consideration out of infinitely many possibilities. We discuss the role that evolutionary mechanisms play in this process. Specifically, we argue that when it comes to developing a global world model, innovation is necessarily ...
Neil R. Bramley +3 more
wiley +1 more source
Evaluating Cache Coherent Shared Virtual Memory for Heterogeneous Multicore Chips [PDF]
, 2013 The trend in industry is towards heterogeneous multicore processors (HMCs), including chips with CPUs and massively-threaded throughput-oriented processors (MTTOPs) such as GPUs.
Hechtman, Blake A., Sorin, Daniel J.
core +2 more sources
Verification of a lazy cache coherence protocol against a weak memory model [PDF]
Formal Methods in Computer-Aided Design, 2017 In this paper, we verify a modern lazy cache coherence protocol, TSO-CC, against the memory consistency model it was designed for, TSO. We achieve this by first showing a weak simulation relation between TSO-CC (with a fixed number of processors) and a ...
C. J. Banks +5 more
semanticscholar +1 more source
Cache Where you Want! Reconciling Predictability and Coherent Caching [PDF]
2020 9th Mediterranean Conference on Embedded Computing (MECO), 2019 Real-time and cyber-physical systems need to interact with and respond to their physical environment in a predictable time. While multicore platforms provide incredible computational power and throughput, they also introduce new sources of unpredictability.
Bansal, Ayoosh +5 more
openaire +3 more sources
Directed Test Generation for Validation of Cache Coherence Protocols
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2019 Computing systems utilize multicore processors with complex cache coherence protocols to meet the increasing need for performance and energy improvement.
Yangdi Lyu +3 more
semanticscholar +1 more source
RPPM : Rapid Performance Prediction of Multithreaded workloads on multicore processors [PDF]
, 2019 Analytical performance modeling is a useful complement to detailed cycle-level simulation to quickly explore the design space in an early design stage. Mechanistic analytical modeling is particularly interesting as it provides deep insight and does not ...
Akram, Shoaib +3 more
core +2 more sources
A Hybrid Coherence Protocol Applied to Multi-channel Direct Connection CMP [PDF]
Jisuanji gongcheng, 2017 Cache coherence protocol impacts the system performance and the demand of bandwidth.Snoopy protocols and directory protocols are widely used in modern server systems,but the former needs large bandwidth while the latter has long latency,so they are not ...
WANG Yunfei,WANG Biao,LI Yuan,SUN Zhanxian
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