Results 41 to 50 of about 489,919 (293)
DCC: A Dependable Cache Coherence Multicore Architecture [PDF]
, 2011 Cache coherence lies at the core of functionally-correct operation of shared memory multicores. Traditional directory-based hardware coherence protocols scale to large core counts, but they incorporate complex logic and directories to track coherence ...
Devadas, Srinivas +3 more
core +1 more source
MRBS: An Area-Efficient Multicast Router for Network-on-Chip Using Buffer Sharing
IEEE Access, 2021 Network-on-chip (NoC) has become the mainstream fabric architecture for chip multiprocessor (CMP) design. Owing to the market-driven advancement of modern applications in CMP, multicast traffic is aggressively increasing to support barrier ...
Min Chae Yang +2 more
doaj +1 more source
Simulating the Network Activity of Modern Manycores
IEEE Access, 2019 Manycore architectures are one of the most promising candidates to reach the exascale. However, the increase in the number of cores on a single die exacerbates the memory wall problem.
Marcos Horro +2 more
doaj +1 more source
Flexible compiler-managed L0 buffers for clustered VLIW processors [PDF]
, 2003 Wire delays are a major concern for current and forthcoming processors. One approach to attack this problem is to divide the processor into semi-independent units referred to as clusters.
Gibert Codina, Enric +2 more
core +1 more source
Modeling Cache Coherence to Expose Interference
Euromicro Conference on Real-Time Systems, 2019 To facilitate programming, most multi-core processors feature automated mechanisms maintaining coherence between each core’s cache. These mechanisms introduce interference, that is, delays caused by concurrent access to a shared resource.
Nathanaël Sensfelder +2 more
semanticscholar +1 more source
Cache Coherence Protocol Design and Simulation Using IES (Invalid Exclusive read/write Shared) State
مجلة بغداد للعلوم, 2017 To improve the efficiency of a processor in recent multiprocessor systems to deal with data, cache memories are used to access data instead of main memory which reduces the latency of delay time.
Baghdad Science Journal
doaj +1 more source
Verification of Programs via Intermediate Interpretation [PDF]
Electronic Proceedings in Theoretical Computer Science, 2017 We explore an approach to verification of programs via program transformation applied to an interpreter of a programming language. A specialization technique known as Turchin's supercompilation is used to specialize some interpreters with respect to the ...
Alexei P. Lisitsa, Andrei P. Nemytykh
doaj +1 more source
Using Flow Specifications of Parameterized Cache Coherence Protocols for Verifying Deadlock Freedom
, 2014 We consider the problem of verifying deadlock freedom for symmetric cache coherence protocols. In particular, we focus on a specific form of deadlock which is useful for the cache coherence protocol domain and consistent with the internal definition of ...
A. Bouajjani +27 more
core +1 more source
Interval simulation: raising the level of abstraction in architectural simulation [PDF]
, 2010 Detailed architectural simulators suffer from a long development cycle and extremely long evaluation times. This longstanding problem is further exacerbated in the multi-core processor era.
Eeckhout, Lieven +2 more
core +3 more sources
Cache coherence using local knowledge [PDF]
Proceedings of the 1993 ACM/IEEE conference on Supercomputing - Supercomputing '93, 1993 Typically, commercially available shared memory machines have addressed the cache coherence problem with hardware strategies based on global inter-cache communication. However, global communication limits scalability and efficiency. "Local knowledge" coherence strategies, which avoid global communication at run-time, offer better scalability, at the ...
E. Darnell, K. Kennedy
openaire +1 more source