Results 51 to 60 of about 489,919 (293)
Mending Fences with Self-Invalidation and Self-Downgrade [PDF]
Logical Methods in Computer Science, 2018 Cache coherence protocols based on self-invalidation and self-downgrade have recently seen increased popularity due to their simplicity, potential performance efficiency, and low energy consumption.
Parosh Aziz Abdulla +5 more
doaj +1 more source
The locality-aware adaptive cache coherence protocol [PDF]
, 2013 Next generation multicore applications will process massive amounts of data with significant sharing. Data movement and management impacts memory access latency and consumes power.
Devadas, Srinivas +2 more
core +2 more sources
Checking Parameterized Promela Models of Cache Coherence Protocols
Труды Института системного программирования РАН, 2018 This paper introduces a method for scalable verification of cache coherence protocols described in the Promela language. Scalability means that resources spent on verification (first of all, machine time and memory) do not depend on the number of ...
V. S. Burenkov, A. S. Kamkin
doaj +1 more source
NCDE: In-Network Caching for Directory Entries to Expedite Data Access in Tiled-Chip Multiprocessors
IEEE Access, 2023 The processing of data-intensive applications, followed by an unprecedented amount of data traffic, drives explosive accesses to the memory subsystem. The overloaded memory subsystem experiences increased data access latency.
Jae Eun Shim, Mingu Kang, Tae Hee Han
doaj +1 more source
ProtoGen: Automatically Generating Directory Cache Coherence Protocols from Atomic Specifications
International Symposium on Computer Architecture, 2018 Designing directory cache coherence protocols is complicated because coherence transactions are not atomic in modern multicore processors. A coherence transaction comprises multiple messages, and these messages can interleave with other conflicting ...
Nicolai Oswald +2 more
semanticscholar +1 more source
Multi-Line Prefetch Covert Channel with Huge Pages
CryptographyModern x86 processors incorporate performance-enhancing features such as prefetching mechanisms, cache coherence protocols, and support for large memory pages (e.g., 2 MB huge pages).
Xinyao Li, Akhilesh Tyagi
doaj +1 more source
A Technique for Parameterized Verification of Cache Coherence Protocols
Труды Института системного программирования РАН, 2018 This paper introduces a technique for scalable functional verification of cache coherence protocols that is based on the verification method, which was previously developed by the author.
V. S. Burenkov
doaj +1 more source
Prediction of Coherence Request Broadcast Range Based on Access Locality [PDF]
Jisuanji gongcheng, 2017 Snoopy protocols and directory protocols are widely used in modern server systems,but the former need large bandwidth,directory protocols have long latency,so they are not suitable for domestic server processor where bandwidth is relatively small and ...
WANG Yunfei,LI Yuan,WANG Biao
doaj +1 more source
VIPS: simple, efficient, and scalable cache coherence [PDF]
, 2016 Directory-based cache coherence is the de-facto standard for scalable shared-memory multi/many-cores and significant effort is invested in reducing its overhead.
Ros, Alberto
core +1 more source
On the tailoring of CAST-32A certification guidance to real COTS multicore architectures [PDF]
, 2017 The use of Commercial Off-The-Shelf (COTS) multicores in real-time industry is on the rise due to multicores' potential performance increase and energy reduction.
Abella Ferrer, Jaume +3 more
core +1 more source