Results 81 to 90 of about 489,919 (293)
Reinforcement Learning-Based Cache Replacement Policies for Multicore Processors
IEEE AccessHigh-performance computing (HPC) systems need to handle ever-increasing data sizes for fast processing and quick response times. However, modern processors’ caches are unable to handle massive amounts of data, leading to significant cache miss ...
Matheus A. Souza, Henrique C. Freitas
doaj +1 more source
, 2011 Directory-based cache coherence is a popular mechanism for chip multiprocessors and multicores. The directory protocol, however, requires multicast for invalidation messages and the collection of acknowledgement messages, which can be expensive in terms ...
Cho, Myong Hyon +4 more
core
On consistency maintenance in service discovery [PDF]
, 2005 Communication and node failures degrade the ability of a service discovery protocol to ensure Users receive the correct service information when the service changes.
Hartel, P.H. +2 more
core +5 more sources
The Political Quarterly, EarlyView.Abstract This article explores how persistent inequality in London can be addressed through a place‐based systems approach, using Feltham in the Borough of Hounslow—one of the capital's most deprived areas—as a case study. It offers a blueprint for community regeneration using a ‘pathways to progression’ education model.
Peter John
wiley +1 more source
Tag Replication and Status Bits Encoding for Enhancing Cache Metadata Reliability
Journal of Electrical and Computer EngineeringOn-chip caches occupy a significant portion of modern processors, making them increasingly vulnerable to soft errors as technology scales. While data arrays often receive robust protection via error-correcting codes (ECCs), metadata elements such as tag ...
Abdulaziz Tabbakh
doaj +1 more source
Comparing IPv7 and Cache Coherence [PDF]
, 2018 The implications of highly-available information have been far-reaching and pervasive. Given the trends in amphibious models, biologists daringly note the exploration of Byzantine fault tolerance.
Mischke, J. (James)
core
Cache coherence verification with TLA% [PDF]
, 1999 We used the specification language TLA+ to analyze the correctness of two cache-coherence protocols for shared-memory multiprocessors based on two generations (EV6 and EV7) of the Alpha processor. A memory model defines the relationship between the values written by one processor and the values read by another, and a cache-coherence protocol ...
Homayoon Akhiani +6 more
openaire +1 more source
Journal of the Royal Anthropological Institute, EarlyView.Drawing on fieldwork conducted in a hospital in Greater Manchester, England in 2016–17, we describe how a set of national health priorities were translated into work for hospital managers and clinicians during a period of significant organizational pressure.
Adam Brisley +2 more
wiley +1 more source
Instruction-Level Execution Migration [PDF]
, 2010 We introduce the Execution Migration Machine (EM²), a novel data-centric multicore memory system architecture based on computation migration. Unlike traditional distributed memory multicores, which rely on complex cache coherence protocols to move the ...
Devadas, Srinivas +2 more
core
Virtual Machine Support for Many-Core Architectures: Decoupling Abstract from Concrete Concurrency Models [PDF]
, 2010 The upcoming many-core architectures require software developers to exploit concurrency to utilize available computational power. Today's high-level language virtual machines (VMs), which are a cornerstone of software development, do not provide ...
A. Peymandoust +56 more
core +3 more sources