Results 1 to 10 of about 295 (146)
Efficient procedure mapping using cache line coloring [PDF]
Proceedings of the ACM SIGPLAN 1997 conference on Programming language design and implementation, 1997 As the gap between memory and processor performance continues to widen, it becomes increasingly important to exploit cache memory eflectively. Both hardware and aoftware approaches can be explored to optimize cache performance. Hardware designers focus on cache organization issues, including replacement policy, associativity, line size and the ...
Amir H. Hashemi +2 more
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Design of Coded Caching Schemes With Linear Subpacketizations Based on Injective Arc Coloring of Regular Digraphs [PDF]
IEEE Transactions on Communications, 2023 Coded caching is an effective technique to decongest the amount of traffic in the backhaul link. In such a scheme, each file hosted in the server is divided into a number of packets to pursue a low transmission rate based on the delicate design of contents cached into users and broadcast messages.
Xianzhang Wu +4 more
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Using Cache-coloring to Mitigate Inter-set Write Variation in Non-volatile Caches [PDF]
, 2013 In recent years, researchers have explored use of non-volatile devices such as STT-RAM (spin torque transfer RAM) for designing on-chip caches, since they provide high density and consume low leakage power. A common limitation of all non-volatile devices is their limited write endurance.
Sparsh Mittal
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Content Placement in Cache Networks Using Graph Coloring [PDF]
IEEE Systems Journal, 2020 Small cell densification is one of the effective ideas addressing the demand for higher capacity in cellular networks. The major problem in such networks is the limited capacity of wireless backhaul links. Caching the popular files in the memories of small cell base stations (SBSs) is an effective solution to this problem. One of the main challenges in
Mostafa Javedankherad +2 more
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Efficient Algorithms for Coded Multicasting in Heterogeneous Caching Networks [PDF]
Entropy, 2019 Coded multicasting has been shown to be a promising approach to significantly improve the performance of content delivery networks with multiple caches downstream of a common multicast link.
Giuseppe Vettigli +5 more
doaj +2 more sources
A Cache-Coloring Based Technique for Saving Leakage Energy In Multitasking Systems [PDF]
, 2013 There has been a significant increase in leakage energy dissipation of CMOS circuits with each technology generation. Further, due to their large size, last level caches (LLCs) spend a large fraction of their energy in the form of leakage energy and hence, addressing this has become extremely important to meet the challenges of chip power budget.
Sparsh Mittal
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Using cache line coloring to perform aggressive procedure inlining [PDF]
ACM SIGARCH Computer Architecture News, 2000 Memory hierarchy performance has always been an important issue in computer architecture design. The likelihood of a bottleneck in the memory hierarchy is increasing, as improvements in microprocessor performance continue to outpace those made in the memory system.
Hakan Aydin, David Kaeli
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Prove your Colorings: Formal Verification of Cache Coloring of Bao Hypervisor [PDF]
Abstract Hypervisors allow sharing of computing resources between applications—possibly of various levels of criticality—that makes them increasingly relevant for modern embedded systems. In this context, memory isolation properties (including low-level cache isolation) are essential to guarantee.
Axel Ferréol +2 more
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A WCET-aware cache coloring technique for reducing interference in real-time systems [PDF]
, 2019 The predictability of a system is the condition to give saferbound on worst case execution timeof real-time tasks which are running on it. Commercial off-the-shelf(COTS) processors are in-creasingly used in embedded systems and contain shared cache memory.
Bouquillon, Fabien +3 more
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Towards practical page coloring-based multicore cache management [PDF]
Proceedings of the 4th ACM European conference on Computer systems, 2009 Modern multi-core processors present new resource management challenges due to the subtle interactions of simultaneously executing processes sharing on-chip resources (particularly the L2 cache). Recent research demonstrates that the operating system may use the page coloring mechanism to control cache partitioning, and consequently to achieve fair and
Xiao Zhang, Sandhya Dwarkadas, Kai Shen
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