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Assessment of Android Network Positioning as an Alternate Source for Robust PNT. [PDF]
Sensors (Basel)Chun J, Spagnolli J, Holmes T, Akos D.
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Optimal partitioning of cache memory
IEEE Transactions on Computers, 1992A model for studying the optimal allocation of cache memory among two or more competing processes is developed and used to show that, for the examples studied, the least recently used (LRU) replacement strategy produces cache allocations that are very close to optimal.
Harold S. Stone +2 more
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Cache-memory interfaces in compressed memory systems
IEEE Transactions on Computers, 2001We consider a number of cache/memory hierarchy design issues in systems with compressed random access memories (C-RAMs) In which compression and decompression occur automatically to and from main memory. Using a C-RAM as main memory, the bulk of main memory contents are stored in a compressed format and dynamically decompressed to handle cache misses ...
Caroline Benveniste +2 more
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The cache DRAM architecture: a DRAM with an on-chip cache memory
IEEE Micro, 1990A DRAM (dynamic RAM) with an on-chip cache, called the cache DRAM, has been proposed and fabricated. It is a hierarchical RAM containing a 1-Mb DRAM for the main memory and an 8-kb SRAM (static RAM) for cache memory. It uses a 1.2- mu m CMOS technology.
Hideto Hidaka +3 more
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ACM Computing Surveys, 1982
The tutorial presents a unified nomenclature for the description of cache memory systems. Using this foundation, examples of existing cache memory systems are detailed and compared.The second presentation discusses a programmable cache memory architecture. In this architecture, intelligence is added to the cache to direct the activity between the cache
Robert P. Cook +3 more
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The tutorial presents a unified nomenclature for the description of cache memory systems. Using this foundation, examples of existing cache memory systems are detailed and compared.The second presentation discusses a programmable cache memory architecture. In this architecture, intelligence is added to the cache to direct the activity between the cache
Robert P. Cook +3 more
openaire +2 more sources
A Modular Assessment for Cache Memories
Proceedings of the 52nd ACM Technical Symposium on Computer Science Education, 2021We construct and evaluate a modular assessment for students' knowledge about CPU cache memories. Caches play a key role in improving performance in modern computing. They are difficult for students to learn, but we have little conceptual or empirical evidence about why.
Suleman Mahmood, Geoffrey L. Herman
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Innovative Architecture for Future Generation High-Performance Processors and Systems IWIA-01, 2001
The new technology of Processing-In-Memory now allows relatively large DRAM memory macros to be positioned on the same die with processing logic. Despite the high bandwidth and low latency possible with such macros, more of both is always better. Classical techniques such as caching are typically used for such performance gains, but at the cost of high
null Zawodny, null Kogge
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The new technology of Processing-In-Memory now allows relatively large DRAM memory macros to be positioned on the same die with processing logic. Despite the high bandwidth and low latency possible with such macros, more of both is always better. Classical techniques such as caching are typically used for such performance gains, but at the cost of high
null Zawodny, null Kogge
openaire +1 more source