Results 221 to 230 of about 132,994 (259)
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Multiprocessors and Cache Memory
2016Increasing demand for high performance has shifted the focus of the designers from single processor to multiprocessor and parallel processing. Another important technique to increase the performance of the overall system is increasing cache memory. Both these techniques play vital role in performance and power consumption.
Jameel Ahmed +3 more
openaire +1 more source
2014
In this chapter we implement a cache based shared memory system and prove that it is sequentially consistent. Sequential consistency means: i) answers of read accesses to the memory system behave as if all accesses to the memory system were performed in some sequential order and ii) this order is consistent with the local order of accesses [7].
Mikhail Kovalev +2 more
openaire +1 more source
In this chapter we implement a cache based shared memory system and prove that it is sequentially consistent. Sequential consistency means: i) answers of read accesses to the memory system behave as if all accesses to the memory system were performed in some sequential order and ii) this order is consistent with the local order of accesses [7].
Mikhail Kovalev +2 more
openaire +1 more source
Eager Memory Cryptography in Caches
2022 55th IEEE/ACM International Symposium on Microarchitecture (MICRO), 2022Xin Wang +2 more
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Fast priority queues for cached memory
ACM Journal of Experimental Algorithmics, 1999The cache hierarchy prevalent in todays high performance processors has to be taken into account in order to design algorithms that perform well in practice. This paper advocates the adaption of external memory algorithms to this purpose. This idea and the practical issues involved are exemplified by engineering a fast priority queue suited to external
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A Large-scale Analysis of Hundreds of In-memory Key-value Cache Clusters at Twitter
ACM Transactions on Storage, 2021Juncheng Yang, Yao Yue
exaly
2015
Due to shrinking feature sizes, cache memories have become highly vulnerable to soft errors. In this thesis, reliability of caches is studied in two ways: ? First, a reliable error protection scheme called Correctable Parity Protected Cache (CPPC) is proposed, which adds error correction capability to a parity-protected cache.
openaire +1 more source
Due to shrinking feature sizes, cache memories have become highly vulnerable to soft errors. In this thesis, reliability of caches is studied in two ways: ? First, a reliable error protection scheme called Correctable Parity Protected Cache (CPPC) is proposed, which adds error correction capability to a parity-protected cache.
openaire +1 more source
2013
Cache memory dirancang secara umum untuk meningkatkan kinerja suatu sistem komputer. Secara logika cache memory berada diantara prosessor dan memory utama yang bertujuan untuk menyediakan data atau instruksi yang akan diolah oleh prosessor. Hal ini menyebabkan waktu yang dibutuhkan menjadi lebih singkat karena prosessor tidak perlu mengambilnya dari ...
openaire +2 more sources
Cache memory dirancang secara umum untuk meningkatkan kinerja suatu sistem komputer. Secara logika cache memory berada diantara prosessor dan memory utama yang bertujuan untuk menyediakan data atau instruksi yang akan diolah oleh prosessor. Hal ini menyebabkan waktu yang dibutuhkan menjadi lebih singkat karena prosessor tidak perlu mengambilnya dari ...
openaire +2 more sources