Results 251 to 260 of about 134,754 (281)
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Optoelectronic-cache memory system architecture

Applied Optics, 1996
We present an investigation of the architecture of an optoelectronic cache that can integrate terabit optical memories with the electronic caches associated with high-performance uniprocessors and multiprocessors. The use of optoelectronic-cache memories enables these terabit technologies to provide transparently low-latency secondary memory with frame
D M, Chiarulli, S P, Levitan
openaire   +2 more sources

Memory registration caching correctness

CCGrid 2005. IEEE International Symposium on Cluster Computing and the Grid, 2005., 2005
Fast and powerful networks are becoming more popular on clusters to support applications including message passing, file systems, and databases. These networks require special treatment by the operating system to obtain high throughput and low latency. In particular, application memory must be pinned and registered in advance of use.
P. Wyckoff, J. Wu
openaire   +1 more source

Cache-Out: Leaking Cache Memory Using Hardware Trojan

IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2020
Data leakage is an important security concern in current systems. Existing data leakage prevention techniques assume that the underlying hardware platform is secure and free from tampering. In this work, we present Cache-Out, a class of system attacks involving hardware compromised with a Trojan embedded in the CPU.
Mohammad Nasim Imtaiz Khan   +2 more
openaire   +1 more source

Reliable cache memories

2015
Due to shrinking feature sizes, cache memories have become highly vulnerable to soft errors. In this thesis, reliability of caches is studied in two ways: ? First, a reliable error protection scheme called Correctable Parity Protected Cache (CPPC) is proposed, which adds error correction capability to a parity-protected cache.
openaire   +1 more source

Scanning Multiple Sequences via Cache Memory

Algorithmica, 2002
zbMATH Open Web Interface contents unavailable due to conflicting licenses.
Mehlhorn, K., Sanders, P.
openaire   +3 more sources

Dynamic Partitioning of Shared Cache Memory

The Journal of Supercomputing, 2004
zbMATH Open Web Interface contents unavailable due to conflicting licenses.
Suh, G. E., Rudolph, L., Devadas, S.
openaire   +2 more sources

Cache memory for microprocessors

ACM SIGARCH Computer Architecture News, 1981
A growth path for current microprocessors is suggested which includes bus enhancements and cache memories. The implications are examined, and several differences from the mainframe world are pointed out.
openaire   +1 more source

Caches and Shared Memory

2014
In this chapter we implement a cache based shared memory system and prove that it is sequentially consistent. Sequential consistency means: i) answers of read accesses to the memory system behave as if all accesses to the memory system were performed in some sequential order and ii) this order is consistent with the local order of accesses [7].
Mikhail Kovalev   +2 more
openaire   +1 more source

Multiprocessors and Cache Memory

2016
Increasing demand for high performance has shifted the focus of the designers from single processor to multiprocessor and parallel processing. Another important technique to increase the performance of the overall system is increasing cache memory. Both these techniques play vital role in performance and power consumption.
Jameel Ahmed   +3 more
openaire   +1 more source

Memory Caching Methods

2011
The objective of data caching and object caching is to improve the performance in accessing multimedia objects from their storage. An efficient cache storage method can have many benefits: First, caching can increase server capacity in serving more streams.
openaire   +1 more source

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