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Cache-memory interfaces in compressed memory systems
IEEE Transactions on Computers, 2001We consider a number of cache/memory hierarchy design issues in systems with compressed random access memories (C-RAMs) In which compression and decompression occur automatically to and from main memory. Using a C-RAM as main memory, the bulk of main memory contents are stored in a compressed format and dynamically decompressed to handle cache misses ...
C.D. Benveniste +2 more
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Cache tag RAM chips simplify cache memory design
Microprocessors and Microsystems, 1990Abstract A few years ago the design of cache memories was of interest only to those designing minicomputers or mainframes. Since the introduction of high-speed microprocessors like the 80386 and the 68030, systems designers have been forced to consider the inclusion of cache memories within their systems.
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Fast priority queues for cached memory
ACM Journal of Experimental Algorithmics, 1999The cache hierarchy prevalent in todays high performance processors has to be taken into account in order to design algorithms that perform well in practice. This paper advocates the adaption of external memory algorithms to this purpose. This idea and the practical issues involved are exemplified by engineering a fast priority queue suited to external
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ACM SIGSAM Bulletin, 2003
The speed of modern computers can be increased by organizing computations so that memory access patterns correspond more closely to the memory cache-loading patterns implemented in the hardware. Rearranging code and data are each possible.
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The speed of modern computers can be increased by organizing computations so that memory access patterns correspond more closely to the memory cache-loading patterns implemented in the hardware. Rearranging code and data are each possible.
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