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Cache Pollution Prevention Mechanism Based on Cache Partition in V-NDN
2020 IEEE/CIC International Conference on Communications in China (ICCC), 2020The information-centric networking, which aims to solve the demand for distributing a large amount of content on the Internet, has proved to be a promising example for various network solutions, such as the Vehicular ad-hoc network (VANET). However, some problems are introduced when the named data networking is combined with V-NDN, such as the cache ...
Jie Zhou +3 more
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Proceedings of ICCD '95 International Conference on Computer Design. VLSI in Computers and Processors, 2002
The bandwidth mismatch of today's high speed processors and standard DRAMS is between a factor of 10 to 50. From 1995 to the year 2000 this mismatch is expected to grow to three orders of magnitude, necessitating greater emphasis for on-chip caches. Today on-chip caches typically consume from 20% to 50% of the total chip area and their cost is mostly a
S.J. Walsh, J.A. Board
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The bandwidth mismatch of today's high speed processors and standard DRAMS is between a factor of 10 to 50. From 1995 to the year 2000 this mismatch is expected to grow to three orders of magnitude, necessitating greater emphasis for on-chip caches. Today on-chip caches typically consume from 20% to 50% of the total chip area and their cost is mostly a
S.J. Walsh, J.A. Board
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International Journal of Modelling and Simulation, 1998
Cache memories are commonly used to reduce the cost of accessing data and instructions in memory. Misses in the cache can severely reduce system performance. It is therefore beneficial to try to anticipate cache misses in an attempt to reduce their frequency.
J.P. Casmira, D.R. Kaeli
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Cache memories are commonly used to reduce the cost of accessing data and instructions in memory. Misses in the cache can severely reduce system performance. It is therefore beneficial to try to anticipate cache misses in an attempt to reduce their frequency.
J.P. Casmira, D.R. Kaeli
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Reducing cache pollution of prefetching in a small data cache
Proceedings 2001 IEEE International Conference on Computer Design: VLSI in Computers and Processors. ICCD 2001, 2002The need for a low power, high performance embedded processor has grown at a very fast pace in recent years. Embedded processors require smaller cache size for low power system-on-a-chip consideration. Decreasing cache size leads to reduced power consumption because a smaller cache has less capacitance from the bit array size as well as smaller drivers
P. Reungsang +4 more
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Cache pollution in Web proxy servers
Proceedings International Parallel and Distributed Processing Symposium, 2004Caching has been used for decades as an effective performance enhancing technique in computer systems. The Least Recently Used (LRU) cache replacement algorithm is a simple and widely used scheme. Proxy caching is a common approach to reduce network traffic and delay in many World Wide Web (WWW) applications.
R. Ayani +2 more
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Unpopular Addresses Should Not Pollute the Cache
2012 13th Symposium on Computer Systems, 2012The "popularity" of a memory word is the fraction of references to this word over the total of memory references in the execution of a program. In this paper we formally define the metric \emph{popularity of reference} and explain the reference patterns of the CommBench programs in terms of this metric.
Renato Carmo, Roberto A. Hexsel
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A Novel Cache Replacement Scheme against Cache Pollution Attack in Content-Centric Networks
2019 IEEE/CIC International Conference on Communications in China (ICCC), 2019In-network cache is a key service of content-centric networks. As an instance of content-centric networks, Named Data Networking (NDN) uses the traditional Least Recently Used (LRU) and Least Frequently Used (LFU) cache replacement strategy, which will cause large storage redundancy.
Ying Liu +4 more
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Detection of cache pollution attacks using randomness checks
2012 IEEE International Conference on Communications (ICC), 2012The Internet plays an increasing role in content dissemination as user-generated contents have exploded recently. Cache servers have been deployed to bypass bottlenecks in the network so that contents can be delivered to end users more efficiently. With caches becoming more embedded in the networks, emerging threats follow naturally.
Hyundo Park, Indra Widjaja, Heejo Lee
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Gini impurity based NDN cache pollution attack defence mechanism
Journal of Information and Optimization Sciences, 2020Name Data Network (NDN) is a futuristic Internet architecture that delivers content based on strategically chosen names and caches content on intermediate routers in the content-delivery path, whic...
Vishwa Pratap Singh, R. L. Ujjwal
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Intelligent Pollution Controlling Mechanism for Peer to Peer Caches
2015 Seventh International Conference on Computational Intelligence, Modelling and Simulation (CIMSim), 2015This paper addresses the problem of cache pollution in P2P (Peer-to-peer) systems. P2P traffic has a significant impact on ISPs as it accounts for more than half of the all traffic. This will cause some negative impact on the Internet like network congestion, high latency. P2P caching is an efficient method for handling this problem.
Raghee Chandran M, G P Sajeev
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